82598EB Datasheet, PDF (282/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - DCA
Figure 3-40. DCA Implementation on FSB System
As Figure 3-40 illustrates, DCA provides a mechanism where the posted write data from an I/O device,
such as an Ethernet NIC, can be placed into CPU cache with a hardware pre-fetch. This mechanism is
initialized at power-on reset. A software device driver for the I/O device configures the I/O device for
DCA and sets up the appropriate CPU ID and bus ID for the device to send data. The device then
encapsulates that information in PCIe TLP headers, in the TAG field, to trigger a hardware pre-fetch by
the MCH to the CPU cache.
DCA implementation is controlled by separated registers (DCA_RXCTRL and DCA_TXCTRL) the
assignment of receive queues to DCA_RXCTL is described in Section 3.5.2, the assignment of transmit
queues to DCA_TXCTL is described in the following – DCA_TXCTRL0 is assigned to transmit queues 0 to
16. DCA_TXCTRL1 is assigned to transmit queues 1 to 17 … DCA_TXCTRL15 is assigned to transmit
queues 15 to 31.
In addition, a DCA_ID register can be found for each port, in order to make visible the function, device,
and bus numbers to the software device driver.
The DCA_RXCTRL and DCA_TXCTRL registers can be written by software on the fly and can be changed
at any time. When software changes the register contents, hardware applies changes only after all the
previous packets in progress for DCA has completed.
The DCA implemented in the 82598 makes use of the MWr method (as opposed to VDM method). This
way, it is consistent with both generations for IOH/MCH.
However, in order to implement DCA, the 82598 has to be aware of the data movement engine version
used (DME1/DME2). The software device driver initializes the 82598 to be aware of the bus
configuration. A new register named DCA_CTRL is used in order to properly define the system
configuration.
There are two modes for DCA implementation:
1. DME1: The DCA target ID is derived from CPU ID
2. DME2: The DCA target ID is derived from APIC ID.
282