82598EB Datasheet, PDF (168/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Hardware EEPROM Sections
3.4.3.1.2 EEPROM Control Word 2 – Address 0x01
Bits
15:12
3
2
Name
Default
Reserved
0000b
Deadlock Timeout
1b
Enable
Core PLL Gate Disable
0b
1
Core Clocks Gate
0b
Disable
0
PCIe PLL Gate Disable
0b
Description
Reserved.
If set, an 82598 that was granted access to the EEPROM that does
not toggle the interface for one second has the grant revoked.
When set, disables the gating of the core PLL in 82598 low power
states.
When set, disables the gating of the core clock in 82598 low power
states.
When set, disables the gating of the PCIe PLL in L1/L2 states.
3.4.3.1.3 EEPROM Control Word 3 – Address 0x38
Bits
15:2
1
Name
Reserved
APM Enable Port 1
0
APM Enable Port 0
Default
0b
0b
0b
Description
Reserved.
Initial value of advanced power management wake up enable in
the General Receive Control register (GRC.APME). Mapped to
GRC.APME of port 1.
Initial value of advanced power management wake up enable in
the General Receive Control register (GRC.APME). Mapped to
GRC.APME of port 0.
3.4.3.2 EEPROM Hardware Pointers
Most of EEPROM words (0x0:0xF) contain hardware pointers to different hardware sections. Note that if
a pointer field is 0xFFFF the appropriate section that the pointer is referring to is not present in the
EEPROM.
3.4.3.2.1 Analog Configuration Sections – Words 0x04:0x05
• Port 0 Configuration Pointer
• Port 1 Configuration Pointer
These sections are loaded after LAN_PWR_GOOD or internal power on reset and contain the analog
default configurations for 82598's analog parts. Words 0x4-0x5 are the pointers for these sections (The
exact EEPROM address, in words).
The structure of all sections is similar as listed in the following table:
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