82598EB Datasheet, PDF (408/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
Rx_lanes_polarity
7:4
0x0¹
Tx_lanes_polarity
3:0
0x0¹
1. Loaded from the EEPROM.
Bit 7 – Changes bits polarity of MAC Rx lane 3
Bit 6 – Changes bits polarity of MAC Rx lane 2
Bit 5 – Changes bits polarity of MAC Rx lane 1
Bit 4 – Changes bits polarity of MAC Rx lane 0
Changes bits polarity if set to 0x1
Bit 3 – Changes bits polarity of mac Tx lane 3.
Bit 2 – Changes bits polarity of mac Tx lane 2.
Bit 1 – Changes bits polarity of mac Tx lane 1.
Bit 0 – Changes bits polarity of mac Tx lane 0.
Changes bits polarity if set to 0x1.
4.4.3.13.23FIFO Status/CNTL Report Register – MACS (0x0429C; RW)
This register reports FIFO status in xgmii_mux.
Field
Rx FIFO overrun
Rx FIFO underrun
Tx FIFO overrun
Tx FIFO underrun
Config FIFO threshold
Reserved
Bit(s)
Initial
Value
31
0b
30
0b
29
0b
28
0b
27:24 0x6
23:16 0x7
Description
Indicates FIFO overrun in xgmii_mux_rx_fifo.
Indicates FIFO underrun in xgmii_mux_rx_fifo.
Indicates FIFO overrun in xgmii_mux_tx_fifo.
Indicates FIFO underrun in xgmii_mux_tx_fifo.
Determines threshold for asynchronous FIFO (generation of data_available
signal is determined by cfg_fifo_th[3:0]).
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
15:4
0x0
3
0b
2
0b
1
0b
0
0b
Reserved
Reserved
Reserved
Reserved
Reserved
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