82598EB Datasheet, PDF (137/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Power Delivery
3.3.1.1 82598 Power States
The 82598 supports the D0 and D3 power states defined in the PCI power management and PCIe
specifications. D0 is divided into two sub-states: D0u (D0 Un-initialized) and D0a (D0 active). In
addition, the 82598 supports a Dr state that is entered when PE_RST_N is asserted (including the
D3cold state).
Figure 3-13 shows the power states and transitions between them.
Figure 3-13. Power Management State Diagram
3.3.1.2 Auxiliary Power Usage
If ADVD3WUC=1b, the 82598 uses the AUX_PWR indication that auxiliary power is available to the
82598, and therefore advertises D3cold Wake Up support. The amount of power required for the
function (which includes the entire NIC) is advertised in the Power Management Data register, which is
loaded from the EEPROM.
If D3cold is supported, the PME_En and PME_Status bits of the Power Management Control/Status
register (PMCSR), as well as their shadow bits in the Wake Up Control (WUC) register are reset only by
the power up reset (detection of power rising).
The only effect of setting AUX_PWR to 1b is advertising D3cold Wake Up support and changing the reset
function of PME_En and PME_Status. AUX_PWR is a strapping option in the 82598.
The 82598 tracks the PME_En bit of the Power Management Control/Status register (PMCSR) and the
Auxiliary (AUX) Power PM Enable bit of the PCIe Device Control register to determine the power it might
consume (and therefore its power state) in the D3cold state (internal Dr state). Note that the actual
amount of power differs between form factors.
The PCIE_Aux bit in the EEPROM determines if the 82598 complies with the auxiliary power regime
defined in the PCIe specification. If set, the 82598 might consume higher aux power according to the
following settings:
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