82598EB Datasheet, PDF (318/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
Software uses this register to even out the delivery of interrupts to the host CPU. The register provides
a guaranteed inter-interrupt delay between interrupts, regardless of network traffic conditions. To
independently validate configuration settings, software should use the following algorithm to convert
the inter-interrupt interval value to the common interrupts/seconds performance metric:
interrupts/sec = (256 10^-9sec x interval)^-1
For example, if the interval is programmed to 500d, the 82598 guarantees the CPU is not interrupted
by it for 128 s from the last interrupt. The maximum observed interrupt rate from the 82598 should
never exceed 7813 interrupts/seconds.
Inversely, the inter-interrupt interval value can be calculated as:
inter-interrupt interval = (256 10^-9sec x interrupts/sec)^-1
The optimal performance setting for this register is system and configuration specific.
4.4.3.3.8 Interrupt Vector Allocation Registers IVAR (0x00900 + 4*n [n=0…24],
RW)
These registers have two modes of operation:
1. In MSI-X mode, these registers define allocation of different interrupt causes to MSI-X vectors.
Each INT_Alloc[i] (i=0…97) field is a byte indexing an entry in the MSI-X Table Structure and MSI-X
PBA Structure.
2. In non MSI-X mode, these registers define the allocation of the Rx/Tx queue interrupt causes to one
of the RTxQ bits in the EICR. Each INT_Alloc[i] (i=0…97) field is a byte indexing the appropriate
RTxQ bit.
31
….24
INT_Alloc[3]
…
23
INT_Alloc[2]
…
16
15
8
7
0
INT_Alloc[1]
INT_Alloc[0]
…
…
…
Reserved
…
Reserved
…
INT_Alloc[97]
…
INT_Alloc[96]
Field
INT_Alloc[0]
Reserved
INT_Alloc
_val[0]
INT_Alloc[1]
Bit(s)
Initial
Value
Description
4:0
0x0
Defines the MSI-X vector assigned to the interrupt cause associated with this entry.
6:5
0x0
Reserved
7
0b
Valid bit for INT_Alloc[0]
12:8
0x0
Defines the MSI-X vector assigned to the interrupt cause associated with this entry,
as defined in.
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