82598EB Datasheet, PDF (116/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Network Interface
3.1.3.2.4 Flash Access Contention
The 82598 implements internal arbitration between Flash accesses initiated through the LAN 0 device
and those initiated through the LAN 1 device. If accesses from both LAN devices are initiated during the
same approximate size window, the first one is served first and only then the next one. Note that the
82598 does not synchronize between the two entities accessing the Flash though contentions caused
from one entity reading and the other modifying the same locations is possible.
To avoid this contention, accesses from both LAN devices should be synchronized using external
software synchronization of the memory or I/O transactions responsible for the access. It might be
possible to ensure contention-avoidance simply by nature of software sequence.
3.1.4 Network Interface
3.1.4.1 10 GbE Interface
The 82598 provides a complete function supporting 10 Gb/s implementations. The device performs all
of the functions required for transmission and reception handling called out in the different standards.
A lower-layer PHY interface is included to attach either to external PMA or Physical Medium Dependent
(PMD) components.
The 10 GbE Attachment Unit Interface (XAUI) supports 12.5 Gb/s operations through its four lane
differential pairs SerDes transceiver paths. When in XAUI mode, the 82598 provides the full PCS and
PMA implementations (through XGXS) including 8b/10b coding, transmit idle randomizer, SerDes,
receive synchronization and lanes Deskew.
This interface has 3.125 Gb/s 4-bit data lanes for both receive and transmit. The clock at transmit
SerDes operates at 3.125 GHz. The receive circuitry performs the clock and data recovery. After each
lane is synchronized, a Deskew mechanism is applied and each lane is aligned properly.
3.1.4.1.1 XGXS – PCS/PMA
The XGMII Extender Sub layer (XGXS) is inserted between the XGMII and XAUI. The source XGXS
converts bytes on an XGMII lane into a self clocked, serial, 8b/10b encoded data stream. Each of the
four encoded lanes is transmitted across one of the four XAUI lanes (byte striping). The destination
XGXS converts the XAUI data stream back into XGMII signals and deskew the four independently
clocked XAUI lanes into the single-clock XGMII. The source XGXS converts XGMII Idle control
characters into an 8b/10b code_sets. The destination XGXS can add to or delete from the interframe as
needed for clock rate disparity compensation prior to converting the interframe code sequence back
into XGMII Idle control characters.
XGXS is the common logic components of PCS and PMA in the 10GBASE-X definition. If external serial
PMA PHY is attached then XGXS is served as an extender (not the final PCS or PMA functions) from the
82598 to external XGXS component.
116