82598EB Datasheet, PDF (111/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Non-Volatile Memory (EEPROM/Flash)
3.1.2.2.3 NC-SI Transactions
The NC-SI link supports both pass through traffic between the BMC and the 82598 LAN functions as
well as configuration traffic between the BMC and the 82598 internal units.
3.1.2.2.3.1 NC-SI-SMBus Mode
NC-SI serves in this mode to transfer pass-through traffic between the BMC and the LAN ports. Packet
structure follows the RMI specification as defined in the NC-SI specification. The following limitations
apply:
• VLAN traffic (if exists) is carried by the packet in its designated area. If VLAN strip is enabled in
an 82598 LAN port, then the VLAN tag must still exist in a VLAN-enabled packet when it is sent
over NC-SI to the BMC.
• The FCS field must be present on any NC-SI packet sent to the BMC. If packet CRC strip is
enabled in the 82598 LAN port, the FCS field must still be there when a packet is sent over NC-SI
to the BMC.
• Flow-control – The 82598 does not initiate flow control over NC-SI (does not send PAUSE
packets). However, the 82598 responds to flow control packets received over NC-SI and meets
the flow-control protocol.
3.1.2.2.3.2 NC-SI Mode
This mode is compatible with the pre-OS sideband DMTF standard.
3.1.3 Non-Volatile Memory (EEPROM/Flash)
This section describes the EEPROM and Flash interfaces supported by 82598.
3.1.3.1 EEPROM
The 82598 uses an EEPROM device to store product configuration information. The EEPROM is divided
into three general regions:
• Hardware Accessed — Loaded by the 82598 hardware after power-up, PCI reset de-assertion, a
D3 to D0 transition, or a software reset.
• Firmware Area — Includes structures used by the firmware for management configuration in its
different modes. Refer to the Intel® 82598 10 GbE Controller System Manageability Interface
application note for configuration values
• Software Accessed — Used by software only. These registers are listed in this document for
convenience and are only for software and are ignored by the 82598.
The EEPROM interface supports Serial Peripheral Interface (SPI) and expects the EEPROM to be capable
of 2 MHz operation.
The 82598 is compatible with many sizes of 4-wire serial EEPROM devices. A 4096-bit serial SPI-
compatible EEPROM can be used. All EEPROMs are accessed in 16-bit words although the EEPROM is
designed to also accept 8-bit data accesses.
The 82598 automatically determines the address size to be used with the SPI EEPROM it is connected to
and sets the EEPROM Size field of the EEPROM/Flash Control (EEC) and Data Register
(EEC.EE_ADDR_SIZE; bit 10). Software uses this size to determine the EEPROM access method. The
exact size of the EEPROM is stored within one of the EEPROM words.
The different EEPROM sizes have two different numbers of address bits (8 bits or 16 bits). As a result,
they must be accessed with a slightly different serial protocol. Software must be aware of this if it
accesses the EEPROM using direct access.
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