82598EB Datasheet, PDF (131/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Specific Function Enable/Disable
2. PCIe is established following the PE_RST_N.
3. BIOS recognizes that a LAN function in the 82598 should be disabled.
4. The BIOS drives the LANx_DIS_N signal to the low level.
5. BIOS issues PE_RST_N or an In-Band PCIe reset.
6. As a result, the 82598 samples the LANx_DIS_N signals, disables the LAN function, and issues an
internal reset to this function.
7. BIOS might start with the device enumeration procedure (the disabled LAN function is invisible –
changed to dummy function).
8. Proceed with normal operation.
9. Re-enabling could be done by driving the LANx_DIS_N signal high and then request the
programmer to issue a warm boot to initialize new bus enumeration.
3.2.2.3.2 Multi-Function Advertisement
If one of the LAN devices is disabled and function 0 is the only active function, the 82598 no longer is a
multi-function device. The 82598 normally reports a 0x80 in the PCI Configuration Header field Header
Type, indicating multi-function capability. However, if a LAN ID is disabled and only function 0 is active,
the 82598 reports a 0x0 in this field to signify single-function capability.
3.2.2.3.3 Interrupt Use
When both LAN devices are enabled, the 82598 uses both the INTA# and INTB# pins for interrupt
reporting. The EEPROM configuration controls which of these two pins are used for each LAN device.
The specific interrupt pin used is reported in the PCI Configuration Header Interrupt Pin field associated
with each LAN device.
However, if either LAN device is disabled, then the INTA# must be used for the remaining LAN device,
therefore the EEPROM configuration must be set accordingly. Under these circumstances, the Interrupt
Pin field of the PCI Header always reports a value of 0x1, indicating INTA# usage.
3.2.2.3.4 Power Reporting
When both LAN devices are enabled, the PCI Power Management Register Block has the capability of
reporting a common power value. The common power value is reflected in the Data field of the PCI
Power Management registers. The value reported as common power is specified via an EEPROM field
and is reflected in the Data field each time the Data_Select field has a value of 0x8 (0x8 = Common
Power Value Select).
When one of LAN ports is disabled and the 82598 appears as a single-function device, the common
power value, if selected, reports 0x0 (undefined value), as common power is undefined for a single-
function device.
3.2.2.4 Device Disable Overview
When both LAN ports are disabled following an Internal Power on Reset/PE_RST_N/ In-Band reset, the
LANx_DIS_N signals should be tied statically to low. At this state the 82598 is disabled, LAN ports are
powered down, all internal clocks are shut down, and the PCIe connection is powered down (similar to
L2 state).
3.2.2.4.1 BIOS Disable the Device at Boot Time by Using Strapping Option
1. Assume that following a power up sequence LANx_DIS_N signals are driven high.
2. The PCIe is established following the PE_RST_N.
3. BIOS recognizes that the 81598 should be disabled.
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