82598EB Datasheet, PDF (398/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
4.4.3.13.8 Flow Control 0 Register – HLREG0 (0x04240, RW)
Field
TXCRCEN
RXCRCSTRP
JUMBOEN
Reserved
TXPADEN
Reserved
Reserved
Reserved
Reserved
LPBK
Bit(s)
Initial
Value
Description
0
1b
Tx CRC Enable
Enables a CRC to be appended to a TX packet if requested.
1b = Enable CRC.
0b = No CRC appended, packets always passed unchanged.
This bit must be set to 1b if the 82598 is enabled to send flow control
frames.
1
1b
Rx CRC Strip
Causes the CRC to be stripped from all packets
1b = Strip CRC.
0b = No CRC.
2
0b
Jumbo Frame Enable
Allows frames up to the size specified in the MHADD (31:16) register.
1b = Enable jumbo frames.
0b = Disable jumbo frames.
9:3
1111111b Reserved and must be set to 1111111b.
10
1b
Tx Pad Frame Enable
Pad short Tx frames to 64 bytes if requested.
1b = Pad frames.
0b = Transmit short frames with no padding.
11
1b
Reserved
Must be set to 1b.
12
0b
Reserved
This bit should not be set to 1b.
13
1b
14
0b
Reserved
Reserved
This bit should not be set to 1b.
15
0b
Loopback
Turn on loopback where transmit data is sent back through the receiver.
To activate loopback the link should be active or AUTOC.FLU should be
set.
1b = Loopback enabled.
0b = Loopback disabled.
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