82598EB Datasheet, PDF (64/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
a. Rx Descriptor Read (four for each LAN port)
b. Tx Descriptor Read (eight for each LAN port)
c. Tx Data Read (up to 16 for each LAN port for manageability)
Note: Completion for separate read requests are not guaranteed to return in order. Completions for
a single read request are guaranteed to return in address order.
3.1.1.6.1 Out of Order Completion Handling
In a split transaction protocol, using multiple read requests in a multi-processor environment, there is a
risk that completions will arrive from the host memory out of order and interleaved. In this case, the
82598 sorts the request completion and transfers them to the Ethernet in the correct order.
3.1.1.7 Transaction Definition and Attributes
3.1.1.7.1 Max Payload Size
The 82598's policy for determining Max Payload Size (MPS) is as follows:
1. Master requests initiated by the 82598 (including completions) limit Max Payload Size to the value
defined for the function issuing the request.
2. Target write accesses to the 82598 are accepted only with a size of one Dword or two Dwords. Write
accesses in the range of three Dwords (MPS) are flagged as unreliable. Write accesses above MPS
are flagged as malformed.
3.1.1.7.2 Traffic Class (TC) and Virtual Channels (VC)
The 82598 only supports TC = 0 and VC = 0 (default).
3.1.1.7.3 Relaxed Ordering
The 82598 takes advantage of the relaxed ordering rules in PCIe. By setting the relaxed ordering bit in
the packet header, the 82598 enables the system to optimize performance in the following cases:
1. Relaxed ordering for descriptor and data reads – When the 82598 masters a read transaction, its
split completion has no ordering relationship with the writes from the CPUs (same direction). It
should be allowed to bypass the writes from the CPUs.
2. Relaxed ordering for receiving data writes – When the 82598 masters receive data writes, it also
enables them to bypass each other in the path to system memory because software does not
process this data until their associated descriptor writes are done.
3. The 82598 cannot relax ordering for descriptor writes or an MSI write.
Relaxed ordering can be used in conjunction with the no-snoop attribute to enable the memory
controller to advance no-snoop writes ahead of earlier snooped writes.
Relaxed ordering is enabled in the 82598 by clearing the RO_DIS bit in the Extended Device Control
(CTRL_EXT) register (0x00018; RW). The actual setting of relaxed ordering is done for LAN traffic by
the host through the DCA registers and for headers redirection through an EEPROM setting.
3.1.1.7.4 No Snoop
The 82598 sets the Snoop_Not_Required attribute bit for master data writes. System logic might
provide a separate path to system memory for non-coherent traffic. The non-coherent path to system
memory provides a higher, more uniform, bandwidth for write requests.
Note: The Snoop Not Required attribute does not alter transaction ordering. Therefore, to achieve
the maximum benefit from snoop not required transactions, it is advisable to set the relaxed
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