82598EB Datasheet, PDF (1/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 Gigabit Ethernet
Controller Datasheet
LAN Access Division
FEATURES
General
 Serial Flash Interface
 4-wire SPI EEPROM Interface
 Configurable LED operation for software or OEM
customization of LED displays
 Protected EEPROM space for private configuration
 Device disable capability
 Package Size - 31 x 31 mm
Networking
 Complies with the 10 Gb/s and 1 Gb/s Ethernet/802.3ap
(KX/KX4) specification
 Complies with the 10 Gb/s Ethernet/802.3ae (XAUI)
specification
 Complies with the 1000BASE-BX specification
 Support for jumbo frames of up to 16 kB
 Auto negotiation clause 73 for supported mode
 CX4 per 802.3ak
 Flow control support: send/receive pause frames and
receive FIFO thresholds
 Statistics for management and RMON
 802.1q VLAN Support
 TCP Segmentation Offload (TSO): up to 256 kB
 IPv6 support for IP/TCP and IP/UDP receive checksum
offload
 Fragmented UDP checksum offload for packet
reassembly
 Message Signaled Interrupts (MSI)
 Message Signaled Interrupts (MSI-X)
 Interrupt throttling control to limit maximum interrupt
rate and improve CPU usage
 Multiple receive queues (RSS) 8 x 8 and 16 x 4
 32 transmit queues
 Dynamic interrupt moderation
 DCA support
 TCP timer interrupts
 No snoop
 Relaxed ordering
 Support for 16 Virtual Machines Device queues (VMDq)
per port
Host Interface
 PCI Express* (PCIe*) Specification v2.0 (2.5 GT/s)
 Bus width - x1, x2, x4, x8
 64-bit address support for systems using more than
four GB of physical memory
MAC FUNCTIONS
 Descriptor ring management hardware for transmit and
receive
 ACPI register set and power down functionality supporting D0
and D3 states
 A mechanism for delaying/reducing transmit interrupts
 Software-controlled global reset bit (resets everything except
the configuration registers)
 Eight Software-Definable Pins (SDP) per port
 Four of the SDP pins can be configured as general-purpose
interrupts
 Wakeup
 IPv6 wake-up filters
 Configurable flexible filter (through EEPROM)
 LAN function disable capability
 Programmable receive buffer of 512 kB, which can be
subdivided to up-to-eight individual packet buffers
 Programmable transmit buffer of 320 kB, subdivided into up-
to-eight individual packet buffers of 40 kB each
 Default Configuration by EEPROM for all LEDs for pre-driver
functionality
Manageability
 Eight VLAN L2 filters
 16 Flex L3 Port filters
 Four flexible TCO filters
 Four L3 address filters (IPv4)
 Advanced pass through-compatible management packet
transmit/receive support
 SMBus interface to an external BMC
 NC-SI interface to an external BMC
 Four L3 address filters (IPv6)
 Four L2 address filters
Revision: 3.23
September 2012