82598EB Datasheet, PDF (389/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
4.4.3.11.9 General Software Semaphore Register – GSSR (0x10160; RW)
Field
SMBITS
Reserved
REGSMP
Bit(s)
9:0
30:10
31
Initial Value
0
0
0
Description
Semaphore Bits
Each bit represents a different software semaphore.
Hardware implementation is read/write registers.
Bits 4:0 are owned by software while bits 9:5 are owned by firmware.
Hardware does not lock access to these bits.
Reserved
Register Semaphore
This bit is used to semaphore the access to this register (not hardware block).
When the bit value is 0b and the register is read, the read transaction shows
0b and the bit is set (next read reads as 1b). Writing 0b to this bit clears it.
A software device driver that reads this register and gets the value of 0b for
this bit locks the access to this register until it clears this bit.
Note: No hardware lock for register access.
SMBITS are reset on Internal Power On Reset or LAN_PWR_GOOD.
Software and firmware synchronize accesses to shared resources in the 82598 through a semaphore
mechanism and a shared configuration register. The SWESMBI bit in the Software Semaphore (SWSM)
register and the EEP_FW_semaphore bit in the Firmware Semaphore (FWSM) register serve as a
semaphore mechanism between software and firmware.
Once software or firmware takes control over the semaphore, it might access the General Software
Semaphore (GSSR) register and claim ownership of a specific resource. The GSSR includes pairs of bits
(one owned by software and the other by firmware), where each pair of bits control a different
resource. A resource is owned by software or firmware when the respective bit is set. Note that it is
illegal to have both bits in a pair set at the same time.
The software/firmware interface uses the following bit assignment convention for the GSSR semaphore
bits.
Field
SW_EEP_SM
SW_PHY_SM0
SW_PHY_SM1
SW_MAC_CSR_SM
SW_FLASH_SM
FW_EEP_SM
FW_PHY_SM0
Bit
Description
0
When set to 1b EEPROM access is owned by software
1
When set to 1b, PHY 0 access is owned by software
2
When set to 1b, PHY 1 access is owned by software
3
When set to 1b, software owns access to shared CSRs
4
Software Flash semaphore
5
When set to 1b, EEPROM access is owned by firmware
6
When set to 1b, PHY 0 access is owned by firmware
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