82598EB Datasheet, PDF (350/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
4.4.3.8 Wake-Up Control Registers
4.4.3.8.1 Wake Up Control Register – WUC (0x05800; RW)
Field
Bit(s) Initial Value
Description
Reserved
0
0b
Reserved
PME_En
1
0b
PME_En
This read/write bit is used by the software device driver to access the PME_En
bit of the Power Management Control/Status Register (PMCSR) without writing
to PCIe configuration space.
PME_Status
2
0b
(RO)
PME_Status
This bit is set when the 82598 receives a wake-up event. It is the same as the
PME_Status bit in the Power Management Control/Status Register (PMCSR).
Writing a 1b to this bit clears it. The PME_Status bit in the PMCSR is also
cleared.
Reserved
3
0b
ADVD3WUC
4
1b¹
Reserved
D3Cold WakeUp Capability Advertisement Enable
When set, D3Cold wakeup capability is advertised based on whether the
AUX_PWR advertises the presence of auxiliary power (yes if AUX_PWR is
indicated, no otherwise). When 0b; however, D3Cold wakeup capability is not
advertised even if AUX_PWR presence is indicated. The data value and initial
value is EEPROM-configurable.
Reserved
31:5
0b
1. Loaded from the EEPROM.
Reserved
The PME_En and PME_Status bits are reset when Internal Power On Reset or LAN_PWR_GOOD is 0b.
When AUX_PWR = 0b or ADVD3WUC=0, these bits are also reset by asserting PE_RST_N.
4.4.3.8.2 Wake Up Filter Control Register – WUFC (0x05808; RW)
Field
LNKC
MAG
EX
MC
BC
ARP
IPV4
Bit(s)
Initial
Value
0
0b
1
0b
2
0b
3
0b
4
0b
5
0b
6
0b
Description
Link Status Change Wake Up Enable
Magic Packet Wake Up Enable
Directed Exact Wake Up Enable
Directed Multicast Wake Up Enable
Broadcast Wake Up Enable
ARP/IPv4 Request Packet Wake Up Enable
Directed IPv4 Packet Wake Up Enable
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