82598EB Datasheet, PDF (298/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
MAC
MAC
0x042D8
ANLPNP2
0x04800
ATLASCTL
Auto Negotiation Link Partner Next
RO
415
Page 2
Core Analog Configuration
RW
415
4.4.3 Register Descriptions
4.4.3.1 General Control Registers
4.4.3.1.1 Device Control Register – CTRL (0x00000/0x00004, RW)
Field
Reserved
PCIe Master
Disable
LRST
Reserved
RST
Reserved
Bit(s)
1:0
2
3
25:4
26
31:27
Initial
Value
Description
0b
Reserved
Write as 0b for future compatibility.
0b
When set, the 82598 blocks new master requests, including manageability
requests, by using this function. Once no master requests are pending by using
this function, the GIO Master Enable Status bit is set.
1b
Link Reset
This bit performs a reset of the MAC, PCS, and auto negotiation functions and the
entire the 82598 10 GbE controller (software reset) resulting in a state nearly
approximating the state following a power-up reset or internal PCIe reset, except
for the system PCI configuration. Normally 0b, writing 1b initiates the reset. This
bit is self-clearing. Also referred to as MAC reset.
0b
Reserved
0b
Device Reset
This bit performs a reset of the 82598, resulting in a state nearly approximating
the state following a power-up reset or internal PCIe reset, except for the system
PCI configuration. Normally 0b, writing 1b initiates the reset. This bit is self-
clearing. Also referred to as a software reset or global reset.
Note: This bit does not reset the MAC, PCS, or auto negotiation functions.
0x0
Reserved
LRST and RST are used to globally reset the 82598 10 GbE controller. This register is provided primarily
as a software mechanism to recover from an indeterminate or suspected hung hardware state. Most
registers (receive, transmit, interrupt, statistics, etc.) and state machines are set to their power-on
reset values, approximating the state following a power-on or PCI reset. However, PCIe configuration
registers are not reset; this leaves the 82598 mapped into system memory space and accessible by a
software device driver.
To ensure that a global device reset has fully completed and that the 82598 responds to subsequent
accesses, programmers must wait approximately 1 ms (after setting) before checking if the bit has
cleared or to access (read or write) device registers.
298