82598EB Datasheet, PDF (182/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Hardware EEPROM Sections
2
SDPVAL[2]
0b
1
SDPVAL[1]
0b
0
SDPVAL[0]
0b
SDP2 Pin – Initial Output Value
Mapped to ESDP.SDP2_DATA.
This bit configures the initial power on value output of SDP2 (when configured as an
output) by configuring the initial hardware value of the SDP2_DATA bit in the ESDP
register following power up.
SDP1 Pin – Initial Output Value
Mapped to ESDP.SDP1_DATA.
This bit configures the initial power on value output of SDP1 (when configured as an
output) by configuring the initial hardware value of the SDP1_DATA bit in the ESDP
register following power up.
SDP0 Pin – Initial Output Value
Mapped to ESDP.SDP0_DATA.
This bit configures the initial power on value output of SDP0 (when configured as an
output) by configuring the initial hardware value of the SDP0_DATA bit in the ESDP
register following power up.
3.4.3.5.5 Filter Control – Offset 7
Bit
15:1
0
Name
Reserved
ADVD3WUC
Default
Description
0b
Reserved.
1b
D3Cold WakeUp Capability Advertisement Enable
When set, D3Cold wakeup capability is advertised based on whether or not
AUX_PWR advertises the presence of auxiliary power.
3.4.3.6 EEPROM MAC 0/1 Sections
Word 0xB points to the LAN MAC configuration defaults of function 0 while word 0xC points to function
1 defaults. Both sections are loaded at the de-assertion of their core master reset.
The structure of both sections is identical as listed in the following table:
Offset
0x1
0x2
0x3
0x4
0x5
High Byte
Low Byte
Section Length = 0x5
Link Mode Configuration
Swap Configuration
Swizzle and Polarity Configuration
Auto Negotiation Default Bits
AUTOC2 Upper Half
Section
3.4.3.6.1
3.4.3.6.2
3.4.3.6.3
3.4.3.6.4
3.4.3.6.5
3.4.3.6.6
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