82598EB Datasheet, PDF (146/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Power Delivery
Table 3-40. D0a to D3 and Back with PE_RST_N
Note
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Writing 11b to the Power State field of the Power Management Control/Status Register (PMCSR) transitions the
82598 to D3. PCIe link transitions to L1 state.
The system can delay an arbitrary amount of time between setting D3 mode and transitioning the link to an L2
or L3 state.
Following link transition, PE_RST_N is asserted.
The system must assert PE_RST_N before stopping the PCIe reference clock. It must also wait t_l2clk after link
transition to L2/L3 before stopping the reference clock.
On assertion of PE_RST_N, the 82598 transitions to Dr state.
The system starts the PCIe reference clock t_PWRGD-CLK before de-assertion PE_RST_N.
The internal PCIe clock is valid and stable t_ppg-clkint from PE_RST_N de-assertion.
The PCIe internal PWRGD signal is asserted tclkpr after the external PE_RST_N signal
Assertion of internal PCIe PWRGD causes the EEPROM to be re-readand disables wake up.
APM wake up mode can be enabled based on what is read from the EEPROM.
Link training starts after t_pgtrn from PE_RST_N de-assertion.
A first PCIe configuration access can arrive after t_pgcfg from PE_RST_N de-assertion.
A first PCI configuration response can be sent after t_pgres from PE_RST_N de-assertion
Writing a 1b to the Memory Access Enable bit in the PCI Command register transitions the 82598 from D0u to D0
state.
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