82598EB Datasheet, PDF (343/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
4.4.3.6.16 Indirection Table – RETA (0x05C00-0x0057C; RW)
The indirection table is a 128-entry table, each entry is 8 bits wide. Each entry stores a 4-bit RSS
output index or a pair of 4-bit indices. The table is configured through the following read/write
registers.
31
Entry 3
….24
23
Entry 2
... ...
16
15
8
7
0
Entry 1
Entry 0
…
…
Entry 127
…
…
…
Field
Entry0
Entry1
Entry2
Entry3
Dword/
Bit(s)
7:0
15:8
23:16
31:24
Initial
Value
0x0
0x0
0x0
0x0
Description
Determines RSS output index or indices for hash value of 0x00.
Determines RSS output index or indices for hash value of 0x01.
Determines RSS output index or indices for hash value of 0x02.
Determines RSS output index or indices for hash value of 0x03.
Each entry (byte) of the indirection table contains the following information:
• Bits [7:4] – RSS output index 1 (optional)
• Bits [3:0] – RSS output index 0
7:4
RSS index 1
3:0
RSS index 0
The contents of the indirection table is not defined following reset of the Memory Configuration
registers. System software must initialize the table prior to enabling multiple receive queues. It might
also update the indirection table during run time. Such updates of the table are not synchronized with
the arrival time of received packets. Therefore, it is not guaranteed that a table update takes effect on
a specific packet boundary.
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