82598EB Datasheet, PDF (252/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Transmit Functionality
DTYP (4)
0011b for this descriptor type
DCMD (8)
TSE (bit 7) – TCP Segmentation Enable
This field indicates a TCP segmentation request. When TSE is set in the first descriptor of a TCP packet,
the hardware uses the corresponding context descriptor in order to perform TCP segmentation.
VLE (bit 6) – VLAN Packet Enable
This field indicates that the packet is a VLAN packet (hardware adds the VLAN Ether type and an 802.1q
VLAN tag to the packet).
DEXT (bit 5) – Descriptor Extension
This field must be 1b to indicate advanced descriptor format (as opposed to legacy)
RS (bit 3) – Report Status
This field signals hardware to report the status information. This is used by software that does in-
memory checks of the transmit descriptors to determine which ones are done. For example, if software
queues up 10 packets to transmit, it can set the RS bit in the last descriptor of the last packet. If
software maintains a list of descriptors with the RS bit set, it can look at them to determine if all
packets up to (and including) the one with the RS bit set have been buffered in the output FIFO.
Looking at the status byte and checking the DD bit do this. If DD is set, the descriptor has been
processed.
Note:
When the RS bit is not used to force write back of descriptors, the 82598 does not write back
descriptor or update the head pointer until half of the internal descriptor cache is available for
write back (32 descriptors). The software device driver must make sure that it doesn't wait
for such a release of those descriptors before handling new ones to the 82598 as it might
result is a deadlock situation. To guarantee that this case doesn't occur, a packet should not
span more than (host ring size – 31) descriptors.
IFCS (bit 1) – Insert FCS
When this field is set, the hardware appends the MAC FCS at the end of the packet. When cleared,
software should calculate the FCS for proper CRC check. There are several cases in which software
must set IFCS as follows:
• Transmission of short packet while padding is enabled by the HLREG0.TXPADEN bit
• Checksum offload is enabled by the either IC TXSM or IXSM bits in the TDESC.DCMD
• VLAN header insertion enabled by the VLE bit in the TDESC.DCMD
• TCP segmentation offload enabled by the TSE bit in the TDESC.DCMD
EOP (bit 0) – End of Packet
Packets can span multiple transmit buffers. EOP indicates whether this is the last buffer for an incoming
packet.
Note:
It is recommended that HLREG0.TXPADEN be enabled when TSE is true since the last frame
can be shorter than 60 bytes – resulting in a bad frame if TXPADEN is disabled. Descriptors
with zero length, transfer no data. Even if they have the RS bit in the command byte set, the
DD field in the status word is not written when hardware processes them.
STA (4)
252