82598EB Datasheet, PDF (75/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
—The Advisory Non-Fatal Error Status bit is set in the Correctable Error Status register to indicate
the occurrence of the advisory error and the Advisory Non-Fatal Error Mask corresponding bit in
the Correctable Error Mask register is checked to determine whether to proceed further with
logging and signaling.
—If the Advisory Non-Fatal Error Mask bit is clear, logging proceeds by setting the corresponding
bit in the Uncorrectable Error Status register, based upon the specific uncorrectable error that's
being reported as an advisory error. If the corresponding Uncorrectable Error bit in the
Uncorrectable Error Mask register is clear, the First Error Pointer and Header Log registers are
updated to log the error, assuming they are not still occupied by a previous unserviced error.
—An ERR_COR Message is sent if the Correctable Error Reporting Enable bit is set in the Device
Control register. An ERROR_NONFATAL message is not sent for this error.
The following uncorrectable non-fatal errors are considered as advisory non-fatal errors:
• A completion with an Unsupported Request or Completer Abort (UR/CA) Status that signals an
uncorrectable error for a non-posted request. If the severity of the UR/CA error is non-fatal, the
completer must handle this case as an advisory non-fatal error.
• When the requestor of a non-posted request times out while waiting for the associated
completion, the requestor is permitted to attempt to recover from the error by issuing a separate
subsequent request or to signal the error without attempting recovery. The requester is permitted
to attempt recovery zero, one, or multiple (finite) times; but it must signal the error (if enabled)
with an uncorrectable error message if no further recovery attempt is made. If the severity of the
completion timeout is non-fatal and the requester elects to attempt recovery by issuing a new
request, the requester must first handle the current error case as an advisory non-fatal error.
• When a receiver receives an unexpected completion and the severity of the unexpected
completion error is non-fatal, the receiver must handle this case as an advisory non-fatal error.
3.1.1.13 Performance Monitoring
The 82598 incorporates PCIe performance monitoring counters to provide common capabilities to
evaluate performance. The device implements four 32-bit counters to correlate between concurrent
measurements of events as well as the sample delay and interval timers. The four 32-bit counters can
also operate in 64-bit mode to count long intervals or payloads.
The list of events supported by the 82598 and the counters Control bits are described in the PCIe
Register section (see Section 4.).
3.1.1.14 Configuration Registers
3.1.1.14.1 PCI Compatibility
PCIe is compatible with existing deployed PCI software. PCIe hardware implementations conform to the
following requirements:
1. All devices are required to support deployed PCI software and must be enumerable as part of a tree
through PCI device enumeration mechanisms.
2. Devices must not require resources (such as address decode ranges and interrupts) beyond those
claimed by PCI resources for operation of existing deployed PCI software.
3. Devices in their default operating state must confirm to PCI ordering and cache coherency rules
from a software viewpoint.
4. PCIe devices must conform to the PCI power management specification and must not require any
register programming for PCI-compatible power management beyond those available through PCI
power management capability registers. Power management is expected to conform to a standard
PCI power management by existing PCI bus drivers.
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