82598EB Datasheet, PDF (381/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
Note:
If the actual length, which is defined by the length field register and the mask bits, is not 8
bytes aligned there might be a case that a packet which is shorter than the actual required
length pass the flexible filter. This can happen due to comparison of up to 7 bytes that come
after the packet but are not a real part of the packet.
The last Dword of each filter contains a length field defining the number of bytes from the beginning of
the packet compared by this filter. If actual packet length is less than the length specified by this field,
the filter fails. Otherwise, it depends on the result of actual byte comparison. The value should not be
greater than 128.
The initial values for the FTFT registers can be loaded from the EEPROM after power-up reset. The FTFT
registers are written by the BMC and not accessible to the host for writing. The registers are used to
filter manageability packets.
Reset – The FTFT registers are cleared on Internal Power On Reset or LAN_PWR_GOOD only.
31
8
31
8
7
0
31
0
Reserved
Reserved
Mask [7:0]
Dword 1
Reserved
Reserved
Mask [15:8]
Dword 3
Reserved
Reserved
Mask [23:16]
Dword 5
Reserved
Reserved
Mask [31:24]
Dword 7
31
0
Dword 0
Dword 2
Dword 4
Dword 6
…………..
31
8
Reserved
Length
31
8
Reserved
Reserved
7
0
Mask
[127:120]
Mask
[127:120]
31
0
Dword 29
Dword 31
31
0
Dword 28
Dword 30
Field
Filter 0 Dword0
Filter 0 Dword1
Filter 0 Mask[7:0]
Reserved
Filter 0 Dword2
Dword
0
1
2
3
4
Address
0x09400
0x09404
0x09408
0x0940C
0x09410
Bit(s)
31:0
31:0
7:0
31:0
Initial Value
X
X
X
X
X
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