82598EB Datasheet, PDF (256/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Transmit Functionality
3.5.3.3.4 Transmit Descriptor Write-Back
The descriptor write-back policy for transmit descriptors is similar to that for receive descriptors with a
few additional factors.
Descriptors are written back in one of three cases:
• TXDCTL[n].WTHRESH = zero and a descriptor which has RS set is ready to be written back
• The corresponding ITR counter has reached zero
• TXDCTL[n].WTHRESH > zero and TXDCTL[n].WTHRESH descriptors have accumulated
For the first condition, write-backs are immediate. This is the default operation.
The other two conditions are only valid if descriptor bursting is enabled. In the second condition, the
ITR counter is used to force a timely write-back of descriptors. The first packet after timer initialization
starts the timer. Timer expiration flushes any accumulated descriptors and sets an interrupt event
(TXDW).
For the final condition, if TXDCTL[n].WTHRESH descriptors are ready for write-back, the write-back is
performed.
Another possibility for descriptor write back is to use the transmit completion head write-back as
explained in Section 3.5.3.7.
3.5.3.4 TCP Segmentation
Hardware TCP segmentation is one of the off-loading options of the TCP/IP stack. This is often referred
to as TSO. This feature enables the TCP/IP stack to pass to the network device driver a message to be
transmitted that is bigger than the Maximum Transmission Unit (MTU) of medium. It is then the
responsibility of the software device driver and hardware to divide the TCP message into MTU size
frames that have appropriate layer 2 (Ethernet), 3 (IP), and 4 (TCP) headers. These headers must
include sequence number, checksum fields, options and flag values as required. Note that some of
these values (such as the checksum values) is unique for each packet of the TCP message, and other
fields such as the source IP address is constant for all packets associated with the TCP message.
CRC appending (HLREG0.TXCRCEN) must be enabled in TCP segmentation mode because CRC is
inserted by hardware. Padding (HLREG0.TXPADEN) must be enabled in TCP segmentation mode, since
the last frame might be shorter than 60 bytes – resulting in a bad frame if TXPADEN is disabled.
The offloading of these mechanisms to the software device driver and the 82598 saves significant CPU
cycles. The software device driver shares the additional tasks to support these options with the 82598.
Although the 82598's TCP segmentation offload implementation was specifically designed to take
advantage of Microsoft's* TCP Segmentation Offload (TSO) feature, the hardware implementation was
made generic enough so that it could also be used to segment traffic from other protocols. For example,
this feature could be used any time it is desirable for hardware to segment a large block of data for
transmission into multiple packets that contain the same generic header.
3.5.3.4.1 Assumptions
The following assumptions apply to the TCP segmentation implementation in the 82598:
• The RS bit operation is not changed. Interrupts are set after data in the buffers pointed to by
individual descriptors are transferred to hardware.
3.5.3.4.2 Transmission Process
The transmission process for regular (non-TCP segmentation packets) involves:
• The protocol stack receives from an application a block of data that is to be transmitted.
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