82598EB Datasheet, PDF (567/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - XAUI, KX/KX4, CX4 and BX Layout Recommendations
If a high-speed signal needs to reference a power plane, then ensure that the height of the secondary
(power) reference plane is at least 3 x h (height) of the primary (ground) reference plane.
8.3.2.6 Dielectric Weave Compensation
Intel recommends slight variations for trace routing to cross the fiberglass weave (or, if traces must be
straight for most of their length, rotate the CAD artwork by 15°).
8.3.2.7 Impedance Discontinuities
Impedance discontinuities cause unwanted signal reflections. Minimize vias (signal through holes) and
other transmission line irregularities. A total of six through holes (a combination of vias and connector
through holes) between the two chips connected by the MAUI interface is a reasonable maximum
budget per differential trace. Unused pads and stub traces should also be avoided.
8.3.2.8 Reducing Circuit Inductance
Traces should be routed over a continuous reference plane with no interruptions. If there are vacant
areas on a reference or power plane, the signal conductors should not cross the vacant area. This
causes impedance mismatches and associated radiated noise levels. Noisy logic grounds should NOT be
located near or under high-speed signals or near sensitive analog pin regions of the LAN silicon. If a
noisy ground area must be near these sensitive signals or IC pins, ensure sufficient decoupling and bulk
capacitance in these areas. Noisy logic and switching power supply grounds can sometimes affect
sensitive DC subsystems such as analog to digital conversion, operational amplifiers, etc. All ground
vias should be connected to every ground plane; and similarly, every power via, to all power planes at
equal potential. This helps reduce circuit inductance. Another recommendation is to physically locate
grounds to minimize the loop area between a signal path and its return path. Rise and fall times should
be as slow as possible. Because signals with fast rise and fall times contain many high frequency
harmonics, which can radiate significantly. The most sensitive signal returns closest to the chassis
ground should be connected together. This will result in a smaller loop area and reduce the likelihood of
crosstalk. The effect of different configurations on the amount of crosstalk can be studied using
electronics modeling software.
8.3.2.9 Signal Isolation
To maintain best signal integrity, keep digital signals far away from the analog traces. A good rule of
thumb is no digital signal should be within 7x to 10x dielectric height of the differential pairs. If digital
signals on other board layers cannot be separated by a ground plane, they should be routed at a right
angle (90 degrees) to the differential pairs. If there is another LAN controller on the board, take care to
keep the differential pairs from that circuit away. Same thing applies to switching regulator traces.
Some rules to follow for signal isolation:
• Separate and group signals by function on separate layers if possible. If possible, maintain a gap
of 7x to 10x dielectric height between all differential pairs (Ethernet) and other nets, but group
associated differential pairs together (Example: Tx with Tx and Rx with Rx).
• Over the length of the trace run, each differential pair should be at least 7x to 10x dielectric
height away from any parallel signal traces.
• Physically group together all components associated with one clock trace to reduce trace length
and radiation.
• Isolate other I/O signals from high-speed signals to minimize crosstalk, which can increase EMI
emission and susceptibility to EMI from other signals.
• Avoid routing high-speed LAN traces near other high-frequency signals associated with a video
controller, cache controller, processor, or other similar devices.
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