82598EB Datasheet, PDF (129/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Specific Function Enable/Disable
3. The wake-up context is defined in the PCI Bus Power Management Interface Specification (sticky
bits). It includes:
a. PME_En bit of the Power Management Control/Status Register (PMCSR).
b. PME_Status bit of the Power Management Control/Status Register (PMCSR).
c. Aux_En in the PCIe registers
d. The device Requester ID (since it is required for the PM_PME TLP).
Note: The shadow copies of these bits in the Wake Up Control (WUC) register are treated
identically.
4. Refers to bits in the WUC register that are not part of the wake-up context (the PME_En and
PME_Status bits).
5. The Wake Up Status (WUS) registers include the following:
a. WUS register
b. Wake Up Packet Length (WUPL).
c. Wake Up Packet Memory (WUPM).
6. The MAC cluster is reset by the appropriate event only if the manageability unit is disabled and the
host is in a low power state with WoL disabled.
3.2.2 Specific Function Enable/Disable
3.2.2.1 General
For a LOM design, it might be desirable for the system to provide BIOS-setup capability for selectively
enabling or disabling LOM devices. This might allow a programmer more control over system resource-
management, avoid conflicts with add-in NIC solutions, etc. The 82598 provides support for selectively
enabling or disabling one or both LAN device(s) in the system.
3.2.2.2 Overview
Device presence (or non-presence) must be established early during BIOS execution, in order to ensure
that BIOS resource-allocation (of interrupts, memory or I/O regions) is done according to devices that
are present only. This is frequently accomplished using a BIOS Configuration Values Driven on Reset
(CVDR) mechanism. The 82598 LAN-disable mechanism is implemented in order to be compatible with
such a solution. The 82598 samples two pins (pin strapping) on reset to determine the LAN-enable
configuration. In addition, the 82598 supports the disabling of one of the PCI functions using EEPROM
configuration.
LAN disabling can be done at two different levels. Either the LAN is disabled completely using the
LANx_DIS_N pin, or the function is not apparent on the PCIe configuration space using a configuration
EEPROM bit. In this case, the LAN function is still available for manageability accesses.
When a particular LAN is fully disabled, all internal clocks to that LAN are disabled. As a result, the
82598 is held in reset and the function presents itself as a dummy device (see Table 3-38).
The sensing of the LANX_Dis_N pins is done after PCIe reset (either PE_RST_N or in-band reset).
As mentioned, one PCI function can be enabled or disabled according to the EEPROM configuration. Two
bits in the EEPROM map indicate which function is disabled. An additional EEPROM bit enables the swap
between the two LAN functions.
Note: Only one function can be disabled through the EEPROM for manageability use.
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