82598EB Datasheet, PDF (207/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Manageability Control Sections
2
Transmit With
When set, sends leading zeros (J/K/ symbols) from CRS_DV assertion to the start of preamble
Leading Zeros
(PHY Mode).
When deasserted, does not send leading zeros (MAC mode).
1
Clear Tx Error
Should be set when Tx path is stuck because of an underflow condition. Cleared by hardware
when released.
0
Enable Tx Pads
When set, the NC-SI TX pads are driving; otherwise, they are isolated.
3.4.5.1.10.5 Tx Mode Control2 (RT_CTRL[31:16]) (Offset 0x4)
Bit
15:0
Name
Reserved
Reserved.
Should be 0b.
Description
3.4.5.1.10.6 MAC Tx Control Reg1 (TxCntrlReg1 (15:0]) (Offset 0x5)
Bit
15:7
Name
Reserved
6
NC-SI_enable
5
Two_part_deferral
4
Append_fcs
3
Pad_enable
2:1
Reserved
0
Tx_ch_en
Description
Reserved.
Should be set to 0b.
Enable the MAC internal NC-SI mode of operation (disables external NC-SI gasket).
When set, performs the optional two part deferral.
When set, computes and appends the FCS on Tx frames.
Pad the TX frames, which are less than the minimum frame size.
Reserved.
Tx Channel Enable
This bit can be used to enable the Tx path of the MAC. This bit is for debug only and the
recommended way to enable the Tx path is via the RT_UCTL_CTRL .TX_enable bit.
3.4.5.1.10.7 NC-SI Settings (NCSISET) (Offset 0x7)
Bit
15:2
Reserved
Name
Reserved.
Should be set to 0b.
Description
207