82598EB Datasheet, PDF (370/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
Field
Q_MAP[0]
Reserved
Q_MAP[1]
Reserved
Q_MAP[2]
Reserved
Q_MAP[3]
Reserved
Bit(s)
Initial
Value
Description
3:0
0x0
Defines the per-queue statistic register that is mapped to this queue.
7:4
0x0
Reserved
11:8
0x0
Defines the per-queue statistic register that is mapped to this queue.
15:12
0x0
Reserved
19:16
0x0
Defines the per-queue statistic register that is mapped to this queue.
23:20
0x0
Reserved
27:24
0x0
Defines the per-queue statistic register that is mapped to this queue.
31:28
0x0
Reserved
4.4.3.9.50 Transmit Queue Statistic Mapping Registers TQSMR (0x7300 + 4*n
[n=0…7], RW)
These registers define the mapping of the transmit queues to the per-queue statistics. This mapping
maps the queues to statistic registers QPTC and QBTC (note that there are 16 of each).
There are 64 queues and only 16 queue statistics registers so each entry refers to a queue and the
value indicates which QPTC and QBTC of the 16 this queue statistics is being counted.
Several queues can be mapped to a single statistic register. Each statistic register counts the number of
packets and bytes of all queues that are mapped to that statistics.
31
….24
Q_MAP[3]
…
23
16
Q_MAP[2]
…
15
8
Q_MAP[1]
…
7
0
Q_MAP[0]
…
...
…
Q_MAP[31]
…
Q_MAP[30]
…
Q_MAP[29]
…
Q_MAP[28]
370