82598EB Datasheet, PDF (97/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
11:10
RO
01b
Active State Link PM Support. Indicates the level of the active state of power
management supported in the 82598. Defined encodings are:
00b = Reserved
01b = L0s entry supported
10b = Reserved
11b = L0s and L1 supported
This field is loaded from the EEPROM PCIe init configuration 3 Word 0x1A.
Bits
14:12
R/W
RO
Default
Description
110b¹
(2 “s – 4 “s)
L0s Exit Latency. Indicates the exit latency from L0s to L0 state.
000b = Less than 64 ns
001b = 64 ns – 128 ns
010b – 128 ns – 256 ns
011b – 256 ns – 512 ns
100b = 512 ns Π 1 “s
101b = 1 “s – 2 “s
110b = 2 “s – 4 “s
111b = Reserved
17:15
RO
111b
L1 Exit Latency. Indicates the exit latency from L1 to L0 state. The 82598 does not
support ASPM L1.
000b = Less than 1 “s
001b = 1 “s – 2 “s
010b = 2 “s – 4 “s
011b = 4 “s – 8 “s
100b = 8 “s – 16 “s
101b = 16 “s – 32 “s
110b = 32 “s – 64 “s
111b = L1 transition not supported.
18
RO
0b
Clock Power Management.
19
RO
0b
Surprise Down Error Reporting Capable.
20
RO
0b
Data Link Layer Link Active Reporting Capable.
21
RO
0b
Link Bandwidth Notification Capability.
23:22
RO
00b
Reserved.
31:24
HwInit
0x0
1. Loaded from the EEPROM.
Port Number. The PCIe port number for the given PCIe link. This field is set in the link
training phase.
Link Control – 2 Byte, Offset 0xB0, (RO) – This register controls PCIe Link specific parameters. There
is a dedicated register per each function.
97