82598EB Datasheet, PDF (579/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Oscillator Solution
8.13.1.2 Programmable Crystal Oscillators
A programmable oscillator can be configured to operate at many frequencies. The device contains a
crystal frequency reference and a phase lock loop (PLL) clock generator. The frequency multipliers and
divisors are controlled by programmable fuses.
PLLs are prone to exhibit frequency jitter. The transmitted signal can also have considerable jitter even
with the programmable oscillator working within its specified frequency tolerance. PLLs must be
designed carefully to lock onto signals over a reasonable frequency range. If the transmitted signal has
high jitter and the receiver’s PLL loses its lock, then bit errors or link loss can occur.
PHY devices are deployed for many different communication applications. Some PHYs contain PLLs with
marginal lock range and cannot tolerate the jitter inherent in data transmission clocked with a
programmable oscillator. The American National Standards Institute (ANSI) X3.263-1995 standard test
method for transmit jitter is not stringent enough to predict PLL-to-PLL lock failures. Therefore, use of
programmable oscillators is generally not recommended.
8.13.2 Oscillator Solution
Choose a clock oscillator with LVPECL output. When connecting the output of the oscillator to an 82598
controller, use AC coupling. 100nF is reasonable value to use. To avoid unwanted reflections on the
clock signal which can lead to non monotonic clock edges, make sure that the transmission line is
correctly terminated. A termination example is shown in Figure 8-5.
Figure 8-9. Reference Oscillator Circuit
Note: The input clock jitter from the oscillator can impact the 82598 clock and its performance. If
output jitter performance is poor, a lower jitter clock oscillator should be chosen.
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