82598EB Datasheet, PDF (313/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
DHER
TCP Timer
Reserved
29
0b
RX/TX Descriptor Handler Error
This bit is set when an unrecoverable error is detected in the descriptor handler
memory for Rx or Tx descriptors.
30
0b
TCP Timer Expired
Activated when the TCP timer reaches its terminal count.
31
0b
Reserved
This register contains frequent interrupt conditions applicable to the 82598. Each time an interrupt-
causing event occurs, the corresponding interrupt bit is set. An interrupt is generated each time one of
the bits in this register is set and the corresponding bit is enabled using the Extended Interrupt Mask
Set/Read register. An interrupt can be delayed by selecting a bit in the Interrupt Throttling register.
Note: The software device driver cannot determine the interrupt cause by using the RxQ and TxQ
bits:
• Receive descriptor write back, receive queue full, receive descriptor minimum threshold hit,
dynamic interrupt moderation for Rx.
• Transmit descriptor write back.
Writing 1b to any bit in the register clears that bit. Writing a 0b to any bit has no effect on that bit.
All register bits are cleared on a register read if GPIE.OCD bit is cleared; if GPIE.OCD bit is set, then
only bits 29:20 are cleared.
Auto-clear can be enabled for any or all of the bits in this register.
4.4.3.3.2 Extended Interrupt Cause Set Register EICS (0x00808, WO)
Field
RTxQ
Reserved
LSC
Reserved
MNG
Reserved
GPI_SDP0
GPI_SDP1
GPI_SDP2
GPI_SDP3
Bit(s)
15:0
19:16
20
21
22
23
24
25
26
27
Initial
Value
0x0
0x0
0b
0b
0b
0b
0b
0b
0b
0b
Description
Set corresponding EICR RTxQ interrupt condition.
Reserved
Set link status change interrupt.
Reserved
Set manageability event interrupt.
Reserved
Set general purpose interrupt on SDP0.
Set general purpose interrupt on SDP1.
Set general purpose interrupt on SDP2.
Set general purpose interrupt on SDP3.
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