82598EB Datasheet, PDF (387/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
4.4.3.11.7 Software Semaphore Register – SWSM (0x10140; RW)
Field
SMBI
SWESMBI
WMNG
Reserved
Bit(s)
Initial
Value
Description
0
0x0
Semaphore Bit
This bit is set by hardware, when this register is read by the software device driver
and cleared when the host driver writes 0b to it.
The first time this register is read, the value is 0b. In the next read, the value is 1b
(hardware mechanism). The value remains 1b until the software device driver clears
it.
This bit is cleared on GIO soft reset.
1
0x0
Software EEPROM Semaphore bit
This bit should be set only by the software device driver (read-only to firmware). The
bit is not set if bit 0 in the FWSM register is set.
The software device driver should set this bit and then read it to see if it was set. If it
was set, it means that the software device driver can read/write from/to the EEPROM.
The software device driver should clear this bit when finishing its EEPROM’s access.
Hardware clears this bit on GIO soft reset.
2
0x0
Wake Manageability Clock
When this bit is set the hardware wakes the manageability clock if gated.
Asserting this bit does not clear the CFG_DONE bit in the EEMNGCTL register.
This bit is self cleared on writes.
31:3
0x0
Reserved.
4.4.3.11.8 Firmware Semaphore Register – FWSM (0x10148; RW)
Field
EEP_FW_
semaphore
FW_mode
Reserved
EEP_reload_
ind
Bit(s)
Initial
Value
Description
0
0b
EEPROM Firmware Semaphore
Firmware should set this bit to 1b before accessing the EEPROM. If software using
the SWSM does not lock the EEPROM, firmware is able to set it to 1b. Firmware
should set it to 0b after completing an EEPROM access.
3:1
0x0
Firmware Mode
Indicates the firmware mode as follows:
0x0 = None (manageability Off).
0x1 = Reserved
0x2 = Pass Through (PT) mode
0x3 = Reserved
0x4 = Host interface enable only.
Else = Reserved
5:4
00b
Reserved
6
0b
EEPROM Reloaded Indication
Set to 1b after firmware reloaded EEPROM.
Cleared by firmware once the Clear Bit host command is received from host
software.
387