82598EB Datasheet, PDF (71/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
Downgrade to x1
82598
82598
Figure 3-5. Lane Downshift in an x4 Reversal Configuration
The lane reversal feature can be controlled by the EEPROM Lane Reversal Disable bit.
3.1.1.11.7 Reset
The PCIe PHY supplies core reset to the 82598. Reset can be caused by the following:
1. Upstream move to hot reset – Inband Mechanism (LTSSM).
2. Recovery failure (LTSSM returns to detect).
3. Upstream component moves to disable.
3.1.1.11.8 Scrambler Disable
The scrambler/de-scrambler functionality in the 82598 can be eliminated by three mechanisms:
1. Upstream, according to the PCIe v2.0 (2.5 GT/s) specification.
2. EPROM bit – Scram_dis.
3. IBIST JTAG CSR.
3.1.1.12 Error Events and Error Reporting
3.1.1.12.1 General Description
PCIe defines two error reporting paradigms: the baseline capability and the Advanced Error Reporting
(AER) capability. Baseline error report capabilities are required of all PCIe devices and define the
minimum error reporting requirements. The AER capability is defined for more robust error reporting
and is implemented with a specific PCIe capability structure. Both mechanisms are supported by the
82598.
Also the SERR# Enable and the Parity Error bits from the legacy command register take part in the
error reporting and logging mechanism.
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