82598EB Datasheet, PDF (124/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

3.2.1.2 Power-Up Timing Diagram
Intel^® 82598EB 10 GbE Controller - Power Up
Figure 3-12. Power-Up Timing Diagram
Table 3-34. References for Power-Up Tuning Diagram
Note
Description
1
Base156 clock is stable t_xog after the power is stable.
2
Internal reset is released after all power supplies are good and t_ppg after Base156 is stable.
3
NVM read starts on the rising edge of internal power on reset or LAN_PWR_GOOD.
4
Sections – EEPROM init and analog configurations are loaded from NVM to configure PLL and core Rx/Tx parameters
and to get indication if manageability/wake up are enabled.
5
PLL clock is stable.
6
Sections EEPROM core and EEPROM MAC are read from NVM to configure MAC, manageability and wake up (if
manageability /wake up enabled).
7
APM wake up and/or manageability active based on NVM contents (if manageability /wake up enabled).
8
The PCIe reference clock is valid t_PWRGD-CLK before de-asserting PE_RST_N (according to PCIe spec).
9
PE_RST_N is de-asserted t_PVPGL after power is stable (according to PCIe spec).
10
De-asserting PE_RST_N causes the NVM to be re-read.
11
Sections EEPROM core, EEPROM MAC, PCIe analog, EEPROM PCIe general configuration, and EEPROM PCIe
configuration space are read from NVM to configure PCIe and MAC.
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