82598EB Datasheet, PDF (312/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
1. Loaded from the EEPROM.
4.4.3.3 Interrupt Registers
4.4.3.3.1 Extended Interrupt Cause Register EICR (0x00800, RC)
Field
RTxQ
Reserved
LSC
Reserved
MNG
Reserved
GPI_SDP0
GPI_SDP1
GPI_SDP2
GPI_SDP3
PBUR
Bit(s)
15:0
19:16
20
21
22
23
24
25
26
27
28
Initial
Value
0x0
0x0
0b
0b
0b
0b
0b
0b
0b
0b
0b
Description
Receive/Transmit Queue Interrupts
One bit per queue or a bundle of queues, activated on receive/transmit queue
events for the corresponding bit, such as:
• Receive Descriptor Write Back
• Receive Descriptor Minimum Threshold hit
• Transmit Descriptor Write Back
The mapping of actual queue the appropriate RTxQ bit is according to the IVAR
registers.
Reserved
Link Status Change
This bit is set each time the link status changes (either from up to down or from
down to up).
Reserved
Manageability Event Detected
Indicates that a manageability event happened. When the 82598 is in power
down mode, the BMC might generate a PME for the same events that would
cause an interrupt when the 82598 is in the D0 state.
Reserved
General Purpose Interrupt on SDP0
If GPI interrupt detection is enabled on this pin (via GPIE), this interrupt cause
is set when the SDP0 is sampled high.
General Purpose Interrupt on SDP1
If GPI interrupt detection is enabled on this pin (via GPIE), this interrupt cause
is set when the SDP1 is sampled high.
General Purpose Interrupt on SDP2
If GPI interrupt detection is enabled on this pin (via GPIE), this interrupt cause
is set when the SDP2 is sampled high.
General Purpose Interrupt on SDP3
If GPI interrupt detection is enabled on this pin (via GPIE), this interrupt cause
is set when the SDP3 is sampled high.
RX/TX Packet Buffer Unrecoverable Error
This bit is set when an unrecoverable error is detected in the packet buffer
memory for Rx or Tx packet.
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