82598EB Datasheet, PDF (565/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - XAUI, KX/KX4, CX4 and BX Layout Recommendations
8.3.2.4 Via Usage
Use vias to optimize signal integrity. Figure 8-2 shows correct via usage. Figure 8-3 shows the type of
topology that should be avoided and can be easily avoided in the board design.
Figure 8-2. Correct Via Usage
Figure 8-3. Incorrect Via Usage
Place ground vias adjacent to signal vias used for the MAUI interface. Do NOT embed vias between the
high-speed signals, but place them adjacent to the signal vias. This helps to create a better GND path
for the return current of the AC signals, which in turn helps address impedance mismatches and EMC
performance.
We recommend that, in the breakout region between the via and the capacitor pad, you target a Z0 for
the via to capacitor trace equal to 50 . This minimizes impedance imbalance.
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