82598EB Datasheet, PDF (380/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
4.4.3.10.8 Manageability MAC Address Low – MMAL (0x5910 + 8*n[n=0..3]; RW)
These registers contain the lower bits of the 48-bit Ethernet address. MMAL registers are written by the
BMC and not accessible to the host for writing. They are used to filter manageability packets.
Reset – MMAL registers are cleared on Internal Power On Reset or LAN_PWR_GOOD only.
The MMAL value should be configured to the register in host order.
Field
Bit(s)
Initial
Value
Description
MMAL
31:0
X¹
Manageability MAC Address Low
The lower 32 bits of the 48-bit Ethernet address.
1. The initial values for this register can be loaded from the EEPROM by the management firmware after power-up reset.
4.4.3.10.9 Manageability MAC Address High – MMAH (0x5914 + 8*n[n=0..3]; RW)
These registers contain the upper bits of the 48-bit Ethernet address. The complete address is {MMAH,
MMAL}. MMAH registers are written by the BMC and not accessible to the host for writing. They are
used to filter manageability packets.
Reset – MMAL registers are cleared on Internal Power On Reset or LAN_PWR_GOOD only.
The MMAH value should be configured to the register in host order.
Field
MMAH
Bit(s)
15:0
Initial
Value
Description
X¹
Manageability MAC Address High
The upper 16 bits of the 48-bit Ethernet address.
Reserved
31:16
0x0
Reserved
Reads as 0x0. Ignored on writes.
1. The initial values for this register can be loaded from the EEPROM by the management firmware after power-up reset.
4.4.3.10.10Flexible TCO Filter Table Registers – FTFT (0x09400-0x097FC; RW)
Each of the Four Flexible TCO Filters table registers (FTFT) contains a 128-byte pattern and a
corresponding 128-bit mask array. If enabled, the first 128 bytes of the received packet are compared
against the non-masked bytes in the FTFT register.
Each 128-byte filter is composed of 32 Dword entries, where each two Dwords are accompanied by an
8-bit mask, one bit per filter byte. The bytes in each two Dwords are written in host order. For example,
byte0 written to bits [7:0], byte1 to bits [15:8] etc. The mask field is set so that bit0 in the mask
masks byte0, bit 1 masks byte 1 etc. A value of one in the mask field means that the appropriate byte
in the filter should be compared to the appropriate byte in the incoming packet.
Note:
The mask field must be 8bytes aligned even if the length field is not 8 bytes aligned as the
hardware implementation compares 8 bytes at a time so it should get extra masks until the
end of the next Qword. Any mask bit that is located after the length should be set to zero
indicating no comparison should be done.
380