82598EB Datasheet, PDF (209/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Device Data/Control Flows
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The descriptors are written back to host memory using PCIe posted writes.
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An interrupt is generated to notify the host driver that the specific packet has been read to the 82598 and the
driver can then release the buffer(s).
Host Memory
packet
Buffer Descriptor
Buffer Descriptor
Ring
PCIe IF
LAN 1
LAN 0
DMA_TX
TDT
DMA_RX
FLEEP
XTX
RXFLT
MAC
MNGMT
Data interfaces
Control Interfaces
External Interfaces
Figure 3-18. Transmit Data Flow
3.5.1.2 Rx Data Flow
Rx data flow provides a high-level description of all data/control transformation steps needed for
receiving Ethernet packets.
Step
1
2
3
4
5
Description
The host creates a descriptor ring and configures one of the 82598’s receive queues with the address location,
length, head, and tail pointers of the ring (one of 64 available Rx queues)
The host initializes descriptor(s) that point to empty data buffer(s). The host places these descriptor(s) in the
correct location at the appropriate Rx ring.
The host updates the appropriate Queue Tail Pointer (RDT).
The 82598’s DMA senses a change of a specific RDT and as a result sends a PCIe request to fetch the
descriptor(s) from host memory.
The descriptor(s) content is received in a PCIe read completion and is written to the appropriate location in the
descriptor queue.
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