82598EB Datasheet, PDF (564/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - XAUI, KX/KX4, CX4 and BX Layout Recommendations
Table 8-1. Pair-to-Pair Spacing
Type
Microstrip
Stripline
Differential
Pair Skew
<5 mils
<5 mils
Differential Pair-to-Pair
Spacing
7 x h; where h=dielectric
height to closest plane
6 x h; where h=dielectric
height to closest plane
Breakout Length
(routes signals from
under package)
<200 mils
<200 mils
Lane-to-
Lane Skew
100 mils
100 mils
XAUI
(maximum
† ^trace
length)
50 cm
50 cm
†
Typical routing requirement over FR4 material. Recommend 0402 capacitor package size for AC coupling. All other XAUI
traces should meet the same spacing requirements as Stripline.
Figure 8-1. Differential Pair Spacing
8.3.2.3 Other High-Speed Signal Routing Practices
These generic layout and routing recommendations are applicable for the MAUI interfaces for the
82598.
In order to keep impedance continuity consistent around via antipad regions, Intel recommends adding
the antipad diameter requirement of >10 mils clearance to vias to GND and PWR. This ensures that the
impedance variance is minimized.
Enforce differential symmetry, even for grounds. Along with ensuring that the MAUI interface is routed
symmetrically in terms of signal routing and balance, we also recommended that GND paths are be
routed symmetrically. This helps to reduce the imbalance that can occur in the different return current
paths.
For the signal trace between the via and AC coupling capacitors on the MAUI interface, there is an
intrinsic impedance mismatch because of required capacitors. To minimize the overall effect of having
vias and AC coupling capacitors, it is recommended that both the via and capacitor layout pad be placed
within 100 mils of each other.
It is best to use a 0402 capacitor or smaller for the AC coupling components on the MAUI interface. The
pad geometries for an 0402 or smaller components lend themselves to maintaining a more consistent
transmission line environment.
Use smallest possible vias on board to optimize the impedance for the MAUI interface.
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