82598EB Datasheet, PDF (232/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Receive Functionality
• Receive Descriptor Base Address registers (RDBA) – This register indicates the start of the
descriptor ring buffer; this 64-bit address is aligned on a 16 byte boundary and is stored in two
consecutive 32-bit registers. Hardware ignores the lower four bits.
• Receive Descriptor Length registers (RDLEN) – This register determines the number of bytes
allocated to the circular buffer. This value must be a multiple of 128 (the maximum cache line
size). Since each descriptor is 16 bytes in length, the total number of receive descriptors is
always a multiple of eight.
• Receive Descriptor Head registers (RDH) – This register holds a value that is an offset from the
base and indicates the in-progress descriptor. There can be up to 32K-8 descriptors in the circular
buffer. Hardware maintains a shadow copy that includes those descriptors completed but not yet
stored in memory.
• Receive Descriptor Tail registers (RDT) – This register holds a value that is an offset from the base
and identifies the location beyond the last descriptor hardware can process. This is the location
where software writes the first new descriptor.
If software statically allocates buffers, and uses a memory read to check for completed descriptors, it
needs to zero the status byte in the descriptor to make it ready for re-use by hardware. This is not a
hardware requirement, but is necessary for performing an in-memory scan.
All registers controlling the descriptor rings behavior should be set before receive is enabled, apart from
the tail registers which are used during the regular flow of data.
3.5.2.9 Header Splitting and Replication
3.5.2.9.1 Purpose
This feature consists of splitting or replicating packet's header to a different memory space. This helps
the host to fetch headers only for processing: headers are replicated through a regular snoop
transaction, in order to be processed by the host CPU. It is recommended to perform this transaction
with the DCA feature enabled (see Section 3.5.6).
The packet (header + payload) is stored in memory through a (optionally) no-snoop transaction. Later,
the data movement engine moves the payload from the driver space to the application memory.
The 82598 supports header splitting in several modes:
• Legacy mode: legacy descriptors are used; headers and payloads are not split
• Advanced mode, no split: advanced descriptors are in use; header and payload are not split
• Advanced mode, split: Advanced descriptors are in use; header and payload are split to different
buffers
• Advanced mode, split: always use header buffer: Advanced descriptors are in use; header and
payload are split to different buffers. If no split is done, the first part of the packet is stored in the
header buffer
• Advanced mode, replication: Advanced descriptors are in use; header is replicated in a separate
buffer, and also in the payload buffer.
• Advanced mode, replication, conditioned by packet size: Advanced descriptors are in use;
replication is performed only if the packet is larger than the header buffer size.
3.5.2.9.2 Description
In Figure 3-24, the header splitting with header replication is described.
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