82598EB Datasheet, PDF (578/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - BIOS Handling of Device Disable
8.12.2 BIOS Handling of Device Disable
Assume that in the following power up sequence the LANx_DIS_N signals are driven high (or it is
already disabled):
1. PCIe link is established following the PE_RST_N.
2. BIOS recognizes that the device should be disabled.
3. BIOS drives the LANx_DIS_N signals to the low level.
4. BIOS issues PE_RST_N or an In-Band PCIe reset.
5. As a result, the device samples the LANx_DIS_N signals and enters the desired device-disable
mode.
6. Re-enable could be done by driving high one of the LANx_DIS_N signals and then issuing a
PE_RST_N to restart the device.
8.12.3 PHY Disable and Device Power Down Signals
The controller has two signals dedicated for powering down a connected external PHY device. These
signals (PHYx_PWRDN_N) can be connected to the power down/disable input of the external PHY or can
be left unconnected.
The controller also provides a DEV_PWRDN_N output signal that can be used to control the power
delivery circuit for the chip based on its internal power state.
For detailed operation of these three signals please consult the Functional Description chapter.
8.13 Oscillator Design Considerations
This section provides information regarding oscillators for use with the 82598 controller.
All designs require a 156.25 MHz external clock source. The 82598 uses this 156.25 MHz source to
generate clocks with frequency up to 3.125 GHz for the high speed interfaces.
The chosen oscillator vendor should be consulted early in the design cycle. Oscillator manufacturers
familiar with networking equipment clock requirements may provide assistance in selecting an
optimum, low-cost solution.
8.13.1 Oscillator Types
8.13.1.1 Fixed Crystal Oscillator
A packaged fixed crystal oscillator comprises an inverter, a quartz crystal, and passive components. The
device renders a consistent square wave output. Oscillators used with microprocessors are supplied in
many configurations and tolerances.
Crystal oscillators can be used in special situations, such as shared clocking among devices. As clock
routing can be difficult to accomplish, it is preferable to provide a separate crystal for each device.
For Intel controllers, it is acceptable to overdrive the internal inverter by connecting a 156.25 MHz
external oscillator to REFCLKIN_P and REFCLKIN_N leads. The oscillator should be specified to drive
CMOS logic levels, and the clock trace to the device should be as short as possible. The chosen device
specifications should call for a 45% (minimum) to 55% (maximum) duty cycle and a ±50 ppm
frequency tolerance.
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