82598EB Datasheet, PDF (141/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Power Delivery
3.3.1.4.2.1 Entry to D0a State
D0a is entered from the D0u state by writing a 1b to the Memory Access Enable or the I/O Access
Enable bit of the PCI Command register. The DMA, MAC, and PHY of the appropriate LAN function are
enabled.
3.3.1.4.3 D3 State (PCI-PM D3hot)
The 82598 transitions to D3 when the system writes a 11b to the Power State field of the Power
Management Control/Status register (PMCSR). Any wake-up filter settings that were enabled before
entering this reset state are maintained. Upon transitioning to D3 state, the 82598 clears the Memory
Access Enable and I/O Access Enable bits of the PCI Command register, which disables memory access
decode. In D3, the 82598 only responds to PCI configuration accesses and does not generate master
cycles.
Configuration and message requests are the only PCIe TLPs accepted by a function in the D3hot state.
All other received requests must be handled as unsupported requests, and all received completions can
optionally be handled as unexpected completions. If an error caused by a received TLP (an unsupported
request) is detected while in D3hot, and reporting is enabled, the link must be returned to L0 if it is not
already in L0 and an error message must be sent. See Section 5.3.1.4.1 in the PCIe v2.0 (2.5 GT/s)
Specification.
A D3 state is followed by either a D0u state (in preparation for a D0a state) or by a transition to Dr
state (PCI-PM D3cold state). To transition back to D0u, the system writes a 00b to the Power State field
of the Power Management Control/Status register (PMCSR). Transition to Dr state is through PE_RST_N
assertion.
3.3.1.4.3.1 Entry to D3 State
Transition to D3 state is through a configuration write to the Power State field of the PCI-PM registers.
Prior to transition from D0 to the D3 state, the software device driver disables scheduling of further
tasks to the 82598; it masks all interrupts, it does not write to the Transmit Descriptor Tail register or to
the Receive Descriptor Tail register and operates the master disable algorithm as defined in
Section 3.3.1.4.3.2. If wake-up capability is needed, the software device driver should set up the
appropriate wake-up registers and the system should write a 1b to the PME_En bit of the Power
Management Control/Status register (PMCSR) or to the Auxiliary (AUX) Power PM Enable bit of the PCIe
Device Control register prior to the transition to D3.
If all PCI functions are programmed into D3 state, the 82598 brings its PCIe link into the L1 link state.
As part of the transition into L1 state, the 82598 suspends scheduling of new TLPs and waits for the
completion of all previous TLPs it has sent. The 82598 clears the Memory Access Enable and I/O Access
Enable bits of the PCI Command register, which disables memory access decode. Any receive packets
that have not been transferred into system memory is kept in the 82598 (and discarded later on D3
exit). Any transmit packets that have not be sent can still be transmitted (assuming the Ethernet link is
up).
In preparation to a possible transition to D3cold state, the software device driver can disable one of the
LAN ports (LAN disable) and/or transition the link(s) to Gb speed (if supported by the network
interface). See Section 3.3.1.3.2 for a description of network interface behavior in this case.
3.3.1.4.3.2 Master Disable
System software can disable master accesses on the PCIe link by either clearing the PCI Bus Master bit
or by bringing the function into a D3 state. From that time on, the 82598 must not issue master
accesses for this function. Due to the full-duplex nature of PCIe, and the pipelined design in the 82598,
it might happen that multiple requests from several functions are pending when the master disable
request arrives. The protocol described in this section insures that a function does not issue master
requests to the PCIe link after its master enable bit is cleared (or after entry to D3 state).
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