82598EB Datasheet, PDF (407/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
4.4.3.13.22SerDes Interface Control Register – SERDESC (0x04298; RW)
Field
swap_rx_lane_0
swap_rx_lane_1
swap_rx_lane_2
swap_rx_lane_3
swap_tx_lane_0
swap_tx_lane_1
swap_tx_lane_2
swap_tx_lane_3
Reserved
Reserved
Bit(s)
Initial
Value
31:3
0
00b¹
29:2
8
27:2
6
25:2
4
23:2
2
01b¹
10b¹
11b¹
00b¹
21:2
0
19:1
8
17:1
6
15:1
2
01b¹
10b¹
11b¹
0x0¹
Description
Determines which core lane is mapped to MAC rx lane 0
00b = Core Rx lane 0 to MAC Rx lane 0.
01b = Core Rx lane 1 to MAC Rx lane 0.
10b = Core Rx lane 2 to MAC Rx lane 0.
11b = Core Rx lane 3 to MAC Rx lane 0.
Determines which core lane is mapped to MAC Rx lane 1.
Determines which core lane is mapped to MAC Rx lane 2.
Determines which core lane is mapped to MAC Rx lane 3.
Determines the core destination Tx lane for MAC Tx Lane 0
00b = MAC tx lane 0 to core tx lane 0.
01b = MAC tx lane 0 to core tx lane 1.
10b = MAC tx lane 0 to core tx lane 2.
11b = MAC tx lane 0 to core tx lane 3.
Determines core destination Tx lane for MAC Tx lane 1.
Determines core destination Tx lane for MAC Tx lane 2.
Determines core destination Tx lane for MAC Tx lane 3.
Reserved
Software should not change the default EEPROM value.
11:8
0x0¹
Reserved
Software should not change the default EEPROM value.
Field
Bit(s)
Initial
Value
Description
407