82598EB Datasheet, PDF (255/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Transmit Functionality
• Transmit Descriptor Tail (TDT) register (31:0) – This register holds a value that is an offset from
the base and indicates the location beyond the last descriptor hardware can process. This is the
location where software writes the first new descriptor.
The base register indicates the start of the circular descriptor queue and the length register indicates
the maximum size of the descriptor ring. The lower seven bits of length are hard-wired to 0b. Byte
addresses within the descriptor buffer are computed as follows: address = base + (ptr * 16), where ptr
is the value in the hardware head or tail register.
The size chosen for the head and tail registers permit a maximum of 64 kB-8 descriptors or
approximately 16 kB packets for the transmit queue given an average of four descriptors per packet.
Once activated, hardware fetches the descriptor indicated by the hardware head register. The hardware
tail register points one beyond the last valid descriptor. Software reads the head register to determine
which packets those logically before the head have been transferred to the on-chip FIFO or transmitted.
All the registers controlling the descriptor rings behaviors should be set before transmit is enabled,
apart from the tail registers which are used during the regular flow of data.
Note: Software can determine if a packet has been sent by setting the RS bit in the transmit
descriptor command field and checking the transmit descriptor DD bit in memory.
In general, hardware prefetches packet data prior to transmission. Hardware typically updates the
value of the head pointer after storing data in the transmit FIFO.
The process of checking for completed packets consists of one of the following:
• Scan memory.
• Read the hardware head register. All packets up to but excluding the one pointed to by head
have been sent or buffered and can be reclaimed.
• Issue an interrupt. An interrupt condition is generated each time a packet was transmitted or
received and a descriptor was write-back or transmit queue goes empty (EICR.RTxQ[0-19]). This
interrupt can either be enabled or masked.
3.5.3.3.3 Transmit Descriptor Fetching
The descriptor processing strategy for transmit descriptors is essentially the same as for receive
descriptors except that a different set of thresholds are used.
When the on-chip buffer is empty, a fetch happens as soon as any descriptors are made available (host
writes to the tail pointer). When the on-chip buffer is nearly empty (TXDCTL[n].PTHRESH), a prefetch is
performed each time enough valid descriptors (TXDCTL[n].HTHRESH) are available in host memory and
no other DMA activity of greater priority is pending (descriptor fetches and write-backs or packet data
transfers).
When the number of descriptors in host memory is greater than the available on-chip descriptor
storage, the 82598 might elect to perform a fetch that is not a multiple of cache line size. The hardware
performs this non-aligned fetch if doing so results in the next descriptor fetch being aligned on a cache
line boundary. This enables the descriptor fetch mechanism to be more efficient in the cases where it
has fallen behind software.
Note:
Software tail updates should be done at packet boundaries. For example, the last valid
descriptor should have its EOP bit set. The last valid descriptor should not be a context
descriptor.
The 82598 NEVER fetches descriptors beyond the descriptor tail pointer.
255