82598EB Datasheet, PDF (88/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
Table 3-20. MSI Message Control Field
Bits
Default
R/W
Description
0
0b
R/W
MSI Enable. 1b = Message Signaled Interrupts. The 82598 generates an MSI for interrupt
assertion instead of INTx signaling.
3:1
000b
RO
Multiple Messages Capable. The 82598 indicates a single requested message per function.
6:4
000b
RO
Multiple Message Enable. The 82598 returns 000b to indicate that it supports a single
message per function.
7
1b
RO
64-bit Capable. A value of 1b indicates that the 82598 is capable of generating 64-bit message
addresses.
15:8
0b
RO
Reserved. Reads as 0b
Message Address Low – 4 Byte, Offset 0x54, (R/W) – Written by the system to indicate the lower 32
bits of the address to use for the MSI memory write transaction. The lower two bits always returns 0b
regardless of the write operation.
Message Address High – 4 Byte, Offset 0x58, (R/W) – Written by the system to indicate the upper 32
bits of the address to use for the MSI memory write transaction.
Message Data – 2 Byte, Offset 0x5C, (R/W) – Written by the system to indicate the lower 16 bits of
the data written in the MSI memory write Dword transaction. The upper 16 bits of the transaction are
written as 0b.
3.1.1.14.6 MSI-X Configuration
The MSI-X capability structure is in Table Note:. Note that more than one MSI-X capability structure per
function is prohibited; however, a function is permitted to have both an MSI and an MSI-X capability
structure.
In contrast to the MSI capability structure, which directly contains all of the control/status information
for the function's vectors, the MSI-X capability structure instead points to an MSI-X table structure and
a MSI-X Pending Bit Array (PBA) structure, each residing in memory space.
Each structure is mapped by a Base Address Register (BAR) belonging to the function that begins at
0x10 in the configuration space. A BAR Indicator Register (BIR) indicates which BAR and a Qword-
aligned offset indicates where the structure begins relative to the base address associated with the
BAR. The BAR can be either 32-bits or 64-bit, but must map to the memory space. A function is
permitted to map both structures with the same BAR or map each structure with a different BAR.
The MSI-X table structure (Table 3-24) typically contains multiple entries, each consisting of several
fields: Message Address, Message Upper Address, Message Data, and Vector Control. Each entry is
capable of specifying a unique vector.
The PBA structure (Table 3-25) contains the function's pending bits, one per table entry, organized as a
packed array of bits within Qwords.
Note: The last Qword will not necessarily be fully populated.MSI-X Capability Structure
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