82598EB Datasheet, PDF (333/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
The 82598 provides multicast filtering for 4096 multicast addresses by providing a single bit entry per
multicast address. The 4096 address locations are organized in a multicast table array – 128 registers
of 32 bits.
Only 12 bits out of the 48-bit destination address are considered as multicast addresses. The 12 bits
can be selected by the MO field of the MCSTCTRL register.
Figure 4-1 shows the multicast lookup algorithm. The destination address shown represents the
internally stored ordering of the received DA. Note that bit 0 is the first bit on the wire.
Figure 4-1. Multicast Lookup Algorithm
4.4.3.6.4 Receive Address Low – RAL (0x05400 + 8*n[n=0..15]; RW)
While "n" is the exact unicast/multicast address entry and it is equals to 0,1,…15.
Field
RAL
Bit(s)
Initial
Value
Description
31:0
X
Receive Address Low
The lower 32 bits of the 48-bit Ethernet address.
These registers contain the lower bits of the 48-bit Ethernet address. All 32 bits are valid. If the
EEPROM is present, the first register (RAL0) is loaded from the EEPROM. The RAL value should be
configured to the register in host order.
4.4.3.6.5 Receive Address High – RAH (0x05404 + 8*n[n=0..15]; RW)
While "n" is the exact unicast/multicast address entry and it is equals to 0,1,…15.
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