82598EB Datasheet, PDF (61/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
3.1.1.4.2 Transaction Types Initiated
Table 3-3. Transaction Types Initiated by the Transaction Layer
Transaction type
Payload Size
FC Type
Configuration Read Request Completion
Dword
CPLH + CPLD
Configuration Write Request Completion
–
CPLH
I/O Read Request Completion
Dword
CPLH + CPLD
I/O Write Request Completion
–
CPLH
Read Request Completion
Dword/Qword
CPLH + CPLD
Memory Read Request
–
NPH
Memory Write Request
Message
<= MAX_PAYLOAD_SIZE
–-
PH + PD
PH
From Client
Configuration Space
Configuration Space
CSR
CSR
CSR
DMA
DMA, MSI/MSI-X
Message Unit/INT/PM/
Error Unit
Note: MAX_PAYLOAD_SIZE is loaded from the EEPROM (either 128 bytes or 256 bytes). Effective MAX_PAYLOAD_SIZE is defined
for each PCI function according to the configuration space register for that function.
3.1.1.4.2.1 Data Alignment
Requests must never specify an address/length combination that causes a memory space access to
cross a 4 kB boundary. The 82598 breaks requests into 4 kB-aligned requests (if needed). This does not
pose any requirement on software. However, if software allocates a buffer across a 4 kB boundary,
hardware issues multiple requests for the buffer. Consider aligning buffers to a 4 kB boundary in cases
where this improves performance.
The general rules for packet alignment are as follows. Note that these apply to all requests (read/write,
snoop and no snoop):
1. The length of a single request does not exceed the PCIe limit of MAX_PAYLOAD_SIZE for write and
MAX_READ_REQ for read.
2. The length of a single request does not exceed 82598 internal limitations.
3. A single request does not span across different memory pages as noted by the 4 kB boundary
alignment above.
If a request can be sent as a single PCIe packet and still meet the general rules for packet alignment,
then it is not broken at the cache line boundary but rather sent as a single packet (the chipset might
break the request along cache line boundaries, but the 82598 will still benefit from better PCIe use).
However, if general rules 1-3 require that the request be broken into two or more packets, then the
request will be broken at the cache line boundary.
61