82598EB Datasheet, PDF (308/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
4.4.3.2.3 Flash Access Register – FLA (0x1001C; RW)
Field
FL_SCK
FL_CE
FL_SI
FL_SO
FL_REQ
FL_GNT
Reserved
FL_BUSY
FL_ER
Bit(s)
Initial
Value
Description
0
0b
Flash Clock Input
When FL_GNT is set to 1b, the FL_SCK output signal is mapped to this bit and
provides the serial clock input to the Flash. Software clocks the Flash via toggling
this bit with successive writes.
1
0b
Flash Chip Select
When FL_GNT is set to 1b, the FL_CE output signal is mapped to the chip select of
the Flash device. Software enables the Flash by writing a 0b to this bit.
2
0b
Flash Data Input
When FL_GNT is set to 1b, the FL_SI output signal is mapped directly to this bit.
Software provides data input to the Flash via writes to this bit.
3
X
Flash Data Output
The FL_SO input signal is mapped directly to this bit in the register and contains the
Flash serial data output. This bit is read-only from a software perspective. Note that
writes to this bit have no effect.
4
0b
Request Flash Access
Software must write a 1b to this bit to get direct Flash access. It has access when
FL_GNT is set to 1b. When software completes the access, it must then write a 0b.
5
0b
Grant Flash Access
When this bit is set to 1b, software can access the Flash using the FL_SCK, FL_CE,
FL_SI, and FL_SO bits.
29:6
0b
Reserved
Reads as 0b.
30
0b
Flash Busy
This bit is set to 1b while a write or an erase to the Flash is in progress, While this bit
is cleared (reads as 0b), software can access to write a new byte to the Flash.
Note: This bit is read-only from a software perspective.
31
0b
Flash Erase Command
This command is sent to the Flash only if bits 5:4 of register EEC are also set to 00b.
This bit is auto-cleared and reads as 0b.
This register provides software direct access to the Flash. Software can control the Flash by successive
writes to this register. Data and address information is clocked into the Flash by software toggling the
FL_SCK bit (0) of this register with FL_CE set to 1b. Data output from the Flash is latched into bit 3 of
this register via the internal 125 MHz clock and can be accessed by software via reads of this register.
In the 82598, the FLA register is only reset at Internal Power On Reset or LAN_PWR_GOOD (as opposed
to legacy devices at software reset).
4.4.3.2.4 Manageability EEPROM Control Register – EEMNGCTL (0x10110; RW)
This register can be read/written by manageability firmware and is read-only to host software.
308