82598EB Datasheet, PDF (352/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
Reserved
FLX0
FLX1
FLX2
FLX3
Reserved
15:9
0x0
16
0b
17
0b
18
0b
19
0b
31:20
0x0
Reserved
Flexible Filter 0 Match
Flexible Filter 1 Match
Flexible Filter 2 Match
Flexible Filter 3 Match
Reserved
This register is used to record statistics about wake-up packets received. If a packet matches multiple
criteria, multiple bits could be set. Writing a 1b to any bit clears that bit.
This register is not cleared when PE_RST_N is asserted. It is only cleared at Internal Power On Reset or
LAN_PWR_GOOD, or when cleared by the software device driver.
4.4.3.8.4 IP Address Valid – IPAV (0x5838; RW)
The IP address valid indicates whether the IP addresses in the IP address table are valid.
Field
V40
V41
V42
V43
Reserved
V60
Reserved
Bit(s)
0
1
2
3
15:4
16
31:17
Initial Value
0
IPv4 Address 0 Valid
0
IPv4 Address 1 Valid
0
IPv4 Address 2 Valid
0
IPv4 Address 3 Valid
0
Reserved
0
IPv6 Address 0 Valid
0
Reserved
Description
4.4.3.8.5 IPv4 Address Table – IP4AT (0x05840 + n*8 [n = 0..3]; RW)
The IPv4 address table stores the four IPv4 addresses for ARP/IPv4 request packet and directed IPv4
packet wake up. It has the following format.
DWORD#
Address
31
0
0
0x5840
IPV4ADDR0
2
0x5848
IPV4ADDR1
352