82598EB Datasheet, PDF (140/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Power Delivery
3.3.1.3.2 Network Interfaces Power Management
The 82598 transitions any of the XAUI interfaces into a low-power state in the following cases:
• The respective LAN function is in LAN disable mode using the LANx_DIS_N pin.
• The 82598 is in Dr State, APM WoL is disabled for the port, ACPI wake is disabled for the port and
pass-through manageability is disabled for the port.
Use of the LAN ports for pass-through manageability follows the following behavior:
• If manageability is disabled (as loaded from the EEPROM), then LAN ports are not allocated for
manageability.
• If manageability is enabled:
—Power-up – Following EEPROM read, a single port is enabled for manageability, running at the
lowest speed supported by the interface. If APM WoL is enabled on a single port, the same port
is used for manageability. Otherwise, manageability protocols (teaming) determine which port
is used.
—D0 state – Both LAN ports are enabled for manageability.
—D3 and Dr states – A single port is enabled for manageability, running at the lowest speed
supported by the interface. If WoL is enabled on a single port, the same port is used for
manageability. Otherwise, manageability protocols (such as teaming) determine which port is
used.
Enabling a port as a result of the above causes an internal reset of the port.
When a XAUI interface is in low-power state, the 82598 asserts the respective PHY0_PWRDN_N or
PHY1_PWRDN_N pin to enable an external PHY device to power down as well.
3.3.1.4 Power States
3.3.1.4.1 D0 Uninitialized State
The D0u state is a low-power state used after PE_RST_N is de-asserted following power up (cold or
warm), on hot reset (in-band reset through PCIe physical layer message) or on D3 exit.
When entering D0u, the 82598 disables Wake ups. If the APM Mode bit in the EEPROM's Control Word 3
is set, then APM Wake Up is enabled.
3.3.1.4.1.1 Entry into D0u State
D0u is reached from either the Dr state (on de-assertion of internal PE_RST_N) or the D3hot state (by
configuration software writing a value of 00b to the Power State field of the PCI PM registers).
De-asserting the internal PE_RST_N means that the entire state of the 82598 is cleared, other than
sticky bits. State is loaded from the EEPROM, followed by establishment of the PCIe link. Once this is
done, configuration software can access the 82598.
On a transition from D3 to D0u state, the 82598 requires that software perform a full re-initialization of
the function including its PCI configuration space.
3.3.1.4.2 D0active State
Once memory space is enabled, the 82598 enters an active state. It can transmit and receive packets if
properly configured by the driver. Any APM Wakeup previously active remains active. The driver can
deactivate APM Wakeup by writing to the Wake Up Control (WUC) register, or activate other wake up
filters by writing to the Wake Up Filter Control (WUFC) register.
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