82598EB Datasheet, PDF (557/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe DC/AC Specification
7.6.6.1 POR_BYPASS (External)
When asserting the POR_BYPASS pad, the 82598 uses the LAN_PWR_GOOD pad as a power-on
indication that disables the Internal Power On detection circuit. Table 7-18 lists the timing for the
External Power On signal.
Table 7-18. Timing for External Power On Signal
Symbol
Title
Description
Min
Max
Units
Tlpgw
LAN_PWR_GOOD
Minimum width for LAN_PWR_GOOD
10
N/A
s
minimum width
Tlpg
LAN_PWR_GOOD low
How long it must be low after voltages
40
80
ms
hold
are in operating range
LAN_PWR_GOOD and POR_BYPPAS are regular digital I/O signals and their characteristics are
described in Section 7.5.1.
Tlpg
+3.3/+1.8/+1.2 V dc
LAN_PWR_GOOD
PE_RST_N
Tlpg-per
Tlpgw
Figure 7-9. LAN_PWR_GOOD Timing
7.6.7 PCIe DC/AC Specification
The transmitter and receiver specifications are available in the PCIe Card Electromechanical
Specification revision 1.1.
7.6.7.1 PCIe Specification (Receiver and Transmitter)
Refer to the PCIe specification.
7.6.7.2 PCIe Specification (Input Clock)
The input clock for PCIe relates to a differential input clock in a frequency of 100 MHz. For more details,
refer to the PCIe Card Electromechanical specifications (refclk specifications).
7.6.8 Reference Clock Specification
The external clock must be 156.25 MHz +/-0.005% (+/- 50 ppm). Refer to Table 7-19. VDD in the table
refers to the 1.2 V dc supply.
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