82598EB Datasheet, PDF (347/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
Since write-back of transmit descriptors is optional (under the control of RS bit in the descriptor), not
all processed descriptors are counted with respect to WTHRESH. Descriptors start accumulating after a
descriptor with the RS bit set. Furthermore, with transmit descriptor bursting enabled, some descriptors
are written back that did not have the RS bit set in their respective descriptors.
For proper operation, the PTHRESH value should be larger than the number of buffers needed to
accommodate a single packet/TSO.
Possible values:
• PTHRESH = 0..32
• WTHRESH = 0..16
• HTHRESH = 0, 4, 8
4.4.3.7.7 Tx Descriptor Completion Write Back Address Low – TDWBAL (0x06038
+ n*0x40[n=0..31]; RW)
Field
Head_WB_En
Reserved
Reserved
HeadWB_Low
Bit(s)
Initial
Value
Description
0
0b
Head Write-Back Enable
When 1b, head write-back is enabled.
When 0b, head write-back is disabled.
1
3:2
31:4
0b
00b
0x00
Reserved
Reserved
Lowest 32 bits of head write-back memory location (Dword-aligned). Last four
bits are always 0000b.
4.4.3.7.8 Tx Descriptor Completion Write Back Address High – TDWBAH
(0x0603C + n*0x40[n=0..31]; RW)
Field
HeadWB_High
Bit(s)
Initial
Value
Description
31:0
0x000
00000
Highest 32 bits of head write-back memory location (for 64-bit addressing)
4.4.3.7.9 DMA TX Control – DTXCTL (0x07E00; RW)
This register controls whether or not the IP Identification field scrolls on 15-bit or 16- bit boundaries in
TSO packets.
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