82598EB Datasheet, PDF (69/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
3.1.1.11.4 L0s Exit Latency
The number of FTS sequences (N_FTS) sent during L0s exit is loaded from the EEPROM into an 8-bit
read-only register.
3.1.1.11.5 Lane-to-Lane De-Skew
A multi-lane link can have many sources of lane-to-lane skew. Although symbols are transmitted
simultaneously on all lanes, they cannot be expected to arrive at the receiver without lane-to-lane
skew. The lane-to-lane skew can include components, which are less than a bit time, bit time units (400
ps for 2.5 Gb), or full symbol time units (4 ns) of skew caused by the retiming repeaters' insert/delete
operations. Receivers use TS1 or TS2 or Skip Ordered Sets (SOS) to perform link de-skew functions.
The 82598 supports de-skew of up to five symbols time (20 ns).
3.1.1.11.6 Lane Reversal
The following lane reversal modes are supported:
• Lane configurations x8, x4, x2, and x1
• Lane reversal in x8 and in x4
• Degraded mode (downshift) from x8 to x4 to x2 to x1 and from x4 to x1, with one restriction – if
lane reversal is executed in x8, then downshift is only to x1 and not to x4
Figure 3-2 through Figure 3-5 shows the lane downshift in both regular and reversal connections as
well as lane connectivity from a system level perspective.
Downgrade to x4
Downgrade to x1
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Figure 3-2. Lane Downshift in an x8 Configuration
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